Datasheet LTC3832, LTC3832-1 (Analog Devices) - 7
| 制造商 | Analog Devices |
| 描述 | High Power Step-Down Synchronous DC/DC Controllers for Low Voltage Operation |
| 页数 / 页 | 24 / 7 — PI FU CTIO S. FREQSET (Pin 11/NA):. VCC (Pin 14/Pin 7):. IMAX (Pin … |
| 文件格式/大小 | PDF / 329 Kb |
| 文件语言 | 英语 |
PI FU CTIO S. FREQSET (Pin 11/NA):. VCC (Pin 14/Pin 7):. IMAX (Pin 12/NA):. PVCC2 (Pin 15/Pin 7):. G2 (Pin 16/Pin 8):
该数据表的模型线
文件文字版本
LTC3832/LTC3832-1
U U U PI FU CTIO S FREQSET (Pin 11/NA):
Frequency Set. Use this pin to
VCC (Pin 14/Pin 7):
Power Supply Input. All low power adjust the free-running frequency of the internal oscillator. internal circuits draw their supply from this pin. Connect With the pin floating, the oscillator runs at about 300kHz. this pin to a clean power supply, separate from the main A resistor from FREQSET to ground speeds up the oscil- VIN supply at the drain of Q1. This pin requires a 4.7µF lator; a resistor to VCC slows it down. bypass capacitor. The LTC3832-1has VCC and PVCC2 tied together at Pin 7 and requires a 10µF bypass capacitor to
IMAX (Pin 12/NA):
Current Limit Threshold Set. IMAX sets GND. the threshold for the internal current limit comparator. If IFB drops below IMAX with G1 on, the LTC3832 goes into
PVCC2 (Pin 15/Pin 7):
Power Supply Input for G2. Connect current limit. IMAX has an internal 12µA pull-down to GND. this pin to the main high power supply. Connect this pin to the main VIN supply at the drain of Q1,
G2 (Pin 16/Pin 8):
Bottom Gate Driver Output. Connect through an external resistor to set the current limit thresh- this pin to the gate of the lower N-channel MOSFET, Q2. old. Connect a 0.1µF decoupling capacitor across this This output swings from PGND to PV resistor to filter switching noise. CC2. It remains low when G1 is high or during shutdown mode. To prevent
IFB (Pin 13/NA):
Current Limit Sense. Connect this pin to output undershoot during a soft-start cycle, G2 is held low the switching node at the source of Q1 and the drain of Q2 until G1 first goes high (FFBG in the Block Diagram). through a 1k resistor. The 1k resistor is required to prevent voltage transients from damaging IFB.This pin is used for sensing the voltage drop across the upper N-channel MOSFET, Q1.
W BLOCK DIAGRA (LTC3832)
DISABLE GATE DRIVE LOGIC AND SHDN 100µs DELAY THERMAL SHUTDOWN INTERNAL POWER DOWN OSCILLATOR PVCC1 – FREQSET S Q G1 PWM R Q PVCC2 + COMP FFBG G2 12µA S Q ENABLE PGND G2 SS QSS POR R VCC MAX ERR – + GND + – FB 18k VREF + 10% SENSE+ VREF 5.7k CC – I SENSE– FB VREF BG + IMAX VREF + 10% 3832 BD 2.2V 12µA QC DISABLE 1.2V ILIM + PVCC1 V – VCC + 2.5V sn3832 3832fs 7
U U U PI FU CTIO S FREQSET (Pin 11/NA):
Frequency Set. Use this pin to
VCC (Pin 14/Pin 7):
Power Supply Input. All low power adjust the free-running frequency of the internal oscillator. internal circuits draw their supply from this pin. Connect With the pin floating, the oscillator runs at about 300kHz. this pin to a clean power supply, separate from the main A resistor from FREQSET to ground speeds up the oscil- VIN supply at the drain of Q1. This pin requires a 4.7µF lator; a resistor to VCC slows it down. bypass capacitor. The LTC3832-1has VCC and PVCC2 tied together at Pin 7 and requires a 10µF bypass capacitor to
IMAX (Pin 12/NA):
Current Limit Threshold Set. IMAX sets GND. the threshold for the internal current limit comparator. If IFB drops below IMAX with G1 on, the LTC3832 goes into
PVCC2 (Pin 15/Pin 7):
Power Supply Input for G2. Connect current limit. IMAX has an internal 12µA pull-down to GND. this pin to the main high power supply. Connect this pin to the main VIN supply at the drain of Q1,
G2 (Pin 16/Pin 8):
Bottom Gate Driver Output. Connect through an external resistor to set the current limit thresh- this pin to the gate of the lower N-channel MOSFET, Q2. old. Connect a 0.1µF decoupling capacitor across this This output swings from PGND to PV resistor to filter switching noise. CC2. It remains low when G1 is high or during shutdown mode. To prevent
IFB (Pin 13/NA):
Current Limit Sense. Connect this pin to output undershoot during a soft-start cycle, G2 is held low the switching node at the source of Q1 and the drain of Q2 until G1 first goes high (FFBG in the Block Diagram). through a 1k resistor. The 1k resistor is required to prevent voltage transients from damaging IFB.This pin is used for sensing the voltage drop across the upper N-channel MOSFET, Q1.
W BLOCK DIAGRA (LTC3832)
DISABLE GATE DRIVE LOGIC AND SHDN 100µs DELAY THERMAL SHUTDOWN INTERNAL POWER DOWN OSCILLATOR PVCC1 – FREQSET S Q G1 PWM R Q PVCC2 + COMP FFBG G2 12µA S Q ENABLE PGND G2 SS QSS POR R VCC MAX ERR – + GND + – FB 18k VREF + 10% SENSE+ VREF 5.7k CC – I SENSE– FB VREF BG + IMAX VREF + 10% 3832 BD 2.2V 12µA QC DISABLE 1.2V ILIM + PVCC1 V – VCC + 2.5V sn3832 3832fs 7