Datasheet AD7768, AD7768-4 (Analog Devices) - 5

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Data Sheet AD7768/AD7768-4 GENERAL DESCRIPTION
The AD7768/AD7768-4 are 8-channel and 4-channel, Within these filter options, the user can improve the dynamic simultaneous sampling sigma-delta (Σ-Δ) analog-to-digital range by selecting from decimation rates of ×32, ×64, ×128, converters (ADCs), respectively, with a Σ-Δ modulator and digital ×256, ×512, and ×1024. The ability to vary the decimation filter per channel, enabling synchronized sampling of ac and dc filtering optimizes noise performance to the required input signals. bandwidth. The AD7768/AD7768-4 achieve 108 dB dynamic range at a Embedded analog functionality on each ADC channel makes maximum input bandwidth of 110.8 kHz, combined with typical design easier, such as a precharge buffer on each analog input performance of ±2 ppm INL, ±50 µV offset error, and ±30 ppm that reduces analog input current and a reference precharge gain error. buffer per channel reduces input current and glitches on the The AD7768/AD7768-4 user can trade off input bandwidth, reference input terminals. output data rate, and power dissipation, and select one of three The device operates with a 5 V AVDD1A and AVDD1B supply, power modes to optimize for noise targets and power a 2.25 V to 5.0 V AVDD2A and AVDD2B supply, and a 2.5 V to consumption. The flexibility of the AD7768/AD7768-4 allows 3.3 V or 1.8 V IOVDD supply (see the 1.8 V IOVDD Operation them to become reusable platforms for low power dc and high section for specific requirements for operating at 1.8 V IOVDD). performance ac measurement modules. The device requires an external reference; the absolute input The AD7768/AD7768-4 have three modes: fast mode (256 kSPS reference voltage range is 1 V to AVDD1 − AVSS. maximum, 110.8 kHz input bandwidth, 51.5 mW per channel), For the purposes of clarity within this document, the AVDD1A median mode (128 kSPS maximum, 55.4 kHz input bandwidth, and AVDD1B supplies are referred to as AVDD1 and the AVDD2A 27.5 mW per channel) and eco mode (32 kSPS maximum, and AVDD2B supplies are referred to as AVDD2. For the negative 13.8 kHz input bandwidth, 9.375 mW per channel). supplies, AVSS refers to the AVSS1A, AVSS1B, AVSS2A, The AD7768/AD7768-4 offer extensive digital filtering AVSS2B, and AVSS pins. capabilities, such as a wideband, low ±0.005 dB pass-band The specified operating temperature range is −40°C to +105°C. ripple, antialiasing low-pass filter with sharp roll-off, and The device is housed in a 10 mm × 10 mm 64-lead LQFP package 105 dB stop band attenuation at the Nyquist frequency. with a 12 mm × 12 mm printed circuit board (PCB) footprint. Frequency domain measurements can use the wideband linear Throughout this data sheet, multifunction pins, such as phase filter. This filter has a flat pass band (±0.005 dB ripple) XTAL2/MCLK, are referred to either by the entire pin name or from dc to 102.4 kHz at 256 kSPS, from dc to 51.2 kHz at by a single function of the pin, for example MCLK, when only 128 kSPS, or from dc to 12.8 kHz at 32 kSPS. that function is relevant. The AD7768/AD7768-4 also offer sinc response via a sinc5 filter, a low latency path for low bandwidth, and low noise measurements. The wideband and sinc5 filters can be selected and run on a per channel basis. Rev. A | Page 5 of 99 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS 1.8 V IOVDD SPECIFICATIONS TIMING SPECIFICATIONS 1.8 V IOVDD TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CLOCKING, SAMPLING TREE, AND POWER SCALING Example of Power vs. Noise Performance Optimization Configuration A Configuration B Clocking Out the ADC Conversion Results (DCLK) NOISE PERFORMANCE AND RESOLUTION APPLICATIONS INFORMATION POWER SUPPLIES Recommended Power Supply Configuration 1.8 V IOVDD Operation Analog Supply Internal Connectivity DEVICE CONFIGURATION Interface Data Format PIN CONTROL Setting the Filter Setting the Decimation Rate Operating Mode Diagnostics Configuration Example Channel Standby SPI CONTROL Accessing the ADC Register Map SPI Interface Details SPI Control Interface Error Handling SPI Reset Configuration SPI CONTROL FUNCTIONALITY Channel Configuration Channel Modes Reset over SPI Control Interface Sleep Mode Channel Standby Clocking Selections MCLK Source Selection Interface Configuration CRC Protection ADC Synchronization over SPI Analog Input Precharge Buffers Reference Precharge Buffers Per Channel Calibration Gain, Offset, and Sync Phase GPIOs SPI CONTROL MODE EXTRA DIAGNOSTIC FEATURES RAM Built In Self Test Revision Identification Number Diagnostic Meter Mode CIRCUIT INFORMATION CORE SIGNAL CHAIN ADC Power Modes ANALOG INPUTS VCM REFERENCE INPUT CLOCK SELECTION DIGITAL FILTERING Sinc5 Filter Wideband Low Ripple Filter DECIMATION RATE CONTROL ANTIALIASING Modulator Sampling Frequency Modulator Chopping Frequency Modulator Saturation Point CALIBRATION Offset Adjustment Gain Adjustment Sync Phase Offset Adjustment DATA INTERFACE SETTING THE FORMAT OF DATA OUTPUT ADC CONVERSION OUTPUT: HEADER AND DATA Chip Error Filter Not Settled Repeated Data Filter Type Filter Saturated Channel ID Data Interface: Standard Conversion Operation Data Interface: One-Shot Conversion Operation Daisy-Chaining Synchronization CRC Check on Data Interface FUNCTIONALITY GPIO FUNCTIONALITY AD7768 REGISTER MAP DETAILS (SPI CONTROL) AD7768 REGISTER MAP CHANNEL STANDBY REGISTER CHANNEL MODE A REGISTER CHANNEL MODE B REGISTER CHANNEL MODE SELECT REGISTER POWER MODE SELECT REGISTER GENERAL DEVICE CONFIGURATION REGISTER DATA CONTROL: SOFT RESET, SYNC, AND SINGLE-SHOT CONTROL REGISTER INTERFACE CONFIGURATION REGISTER DIGITAL FILTER RAM BUILT IN SELF TEST (BIST) REGISTER STATUS REGISTER REVISION IDENTIFICATION REGISTER GPIO CONTROL REGISTER GPIO WRITE DATA REGISTER GPIO READ DATA REGISTER ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 0 TO CHANNEL 3 ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 4 TO CHANNEL 7 POSITIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER NEGATIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER OFFSET REGISTERS GAIN REGISTERS SYNC PHASE OFFSET REGISTERS ADC DIAGNOSTIC RECEIVE SELECT REGISTER ADC DIAGNOSTIC CONTROL REGISTER MODULATOR DELAY CONTROL REGISTER CHOPPING CONTROL REGISTER AD7768-4 REGISTER MAP DETAILS (SPI CONTROL) AD7768-4 REGISTER MAP CHANNEL STANDBY REGISTER CHANNEL MODE A REGISTER CHANNEL MODE B REGISTER CHANNEL MODE SELECT REGISTER POWER MODE SELECT REGISTER GENERAL DEVICE CONFIGURATION REGISTER DATA CONTROL: SOFT RESET, SYNC, AND SINGLE-SHOT CONTROL REGISTER INTERFACE CONFIGURATION REGISTER DIGITAL FILTER RAM BUILT IN SELF TEST (BIST) REGISTER STATUS REGISTER REVISION IDENTIFICATION REGISTER GPIO CONTROL REGISTER GPIO WRITE DATA REGISTER GPIO READ DATA REGISTER ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 0 AND CHANNEL 1 ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 2 AND CHANNEL 3 POSITIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER NEGATIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER OFFSET REGISTERS GAIN REGISTERS SYNC PHASE OFFSET REGISTERS ADC DIAGNOSTIC RECEIVE SELECT REGISTER ADC DIAGNOSTIC CONTROL REGISTER MODULATOR DELAY CONTROL REGISTER CHOPPING CONTROL REGISTER OUTLINE DIMENSIONS ORDERING GUIDE