Datasheet AD7768, AD7768-4 (Analog Devices) - 10

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AD7768/AD7768-4 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit
IOVDD Current Wideband filter2 10 11.1 mA Wideband filter, SPI mode only; 9 10 mA Channel Mode A set to sinc5 filter8 Sinc5 filter2 6.5 7.6 mA AD7768 and AD7768-4—Two Serial peripheral interface (SPI) control Channels Active2 mode only; see the Channel Standby section for details on disabling channels Fast Mode AVDD1 Current Reference precharge buffers off/on 9.3/14.7 10.5/16.6 mA AVDD2 Current 9.5 10.5 mA IOVDD Current Wideband filter 33.7 36.3 mA Wideband filter; disabled channels in 23.4 25.5 mA Channel Mode A, and set to sinc5 filter mode8 Sinc5 filter 11.9 13.3 mA Median Mode AVDD1 Current Reference precharge buffers off/on 4.8/7.5 5.5/8.6 mA AVDD2 Current 5.5 6.2 mA IOVDD Current Wideband filter 19.4 21.1 mA Wideband filter; disabled channels in 14.1 15.5 mA Channel Mode A, and set to sinc5 filter mode8 Sinc5 filter 8.5 9.6 mA Eco Mode AVDD1 Current Reference precharge buffers off/on 1.52/2.2 1.77/2.6 mA AVDD2 Current 2.4 3 mA IOVDD Current Wideband filter 8.6 9.7 mA Wideband filter; disabled channels in 7.2 8 mA Channel Mode A, and set to sinc5 filter mode8 Sinc5 filter 5.8 6.7 mA Standby Mode Al channels disabled (sinc5 filter enabled) 6.5 8 mA Sleep Mode2 Full power-down (SPI control mode only) 0.73 1.2 mA Crystal Excitation Current Extra current in IOVDD when using an 540 µA external crystal compared to using the CMOS MCLK POWER DISSIPATION External CMOS MCLK, all channels active, MCLK = 32.768 MHz, all channels in Channel Mode A except where otherwise specified Full Operating Mode Analog precharge buffers on AD7768 Wideband Filter Fast AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V, 412 446 mW reference precharge buffers off2 AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V, 600 645 mW reference precharge buffers on2 AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD = 631 681 mW 3.6 V, reference precharge buffers off Median AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V, 220 240 mW reference precharge buffers off2 AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V, 320 345 mW reference precharge buffers on2 AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD = 341 372 mW 3.6 V, reference precharge buffers off Rev. A | Page 10 of 99 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS 1.8 V IOVDD SPECIFICATIONS TIMING SPECIFICATIONS 1.8 V IOVDD TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CLOCKING, SAMPLING TREE, AND POWER SCALING Example of Power vs. Noise Performance Optimization Configuration A Configuration B Clocking Out the ADC Conversion Results (DCLK) NOISE PERFORMANCE AND RESOLUTION APPLICATIONS INFORMATION POWER SUPPLIES Recommended Power Supply Configuration 1.8 V IOVDD Operation Analog Supply Internal Connectivity DEVICE CONFIGURATION Interface Data Format PIN CONTROL Setting the Filter Setting the Decimation Rate Operating Mode Diagnostics Configuration Example Channel Standby SPI CONTROL Accessing the ADC Register Map SPI Interface Details SPI Control Interface Error Handling SPI Reset Configuration SPI CONTROL FUNCTIONALITY Channel Configuration Channel Modes Reset over SPI Control Interface Sleep Mode Channel Standby Clocking Selections MCLK Source Selection Interface Configuration CRC Protection ADC Synchronization over SPI Analog Input Precharge Buffers Reference Precharge Buffers Per Channel Calibration Gain, Offset, and Sync Phase GPIOs SPI CONTROL MODE EXTRA DIAGNOSTIC FEATURES RAM Built In Self Test Revision Identification Number Diagnostic Meter Mode CIRCUIT INFORMATION CORE SIGNAL CHAIN ADC Power Modes ANALOG INPUTS VCM REFERENCE INPUT CLOCK SELECTION DIGITAL FILTERING Sinc5 Filter Wideband Low Ripple Filter DECIMATION RATE CONTROL ANTIALIASING Modulator Sampling Frequency Modulator Chopping Frequency Modulator Saturation Point CALIBRATION Offset Adjustment Gain Adjustment Sync Phase Offset Adjustment DATA INTERFACE SETTING THE FORMAT OF DATA OUTPUT ADC CONVERSION OUTPUT: HEADER AND DATA Chip Error Filter Not Settled Repeated Data Filter Type Filter Saturated Channel ID Data Interface: Standard Conversion Operation Data Interface: One-Shot Conversion Operation Daisy-Chaining Synchronization CRC Check on Data Interface FUNCTIONALITY GPIO FUNCTIONALITY AD7768 REGISTER MAP DETAILS (SPI CONTROL) AD7768 REGISTER MAP CHANNEL STANDBY REGISTER CHANNEL MODE A REGISTER CHANNEL MODE B REGISTER CHANNEL MODE SELECT REGISTER POWER MODE SELECT REGISTER GENERAL DEVICE CONFIGURATION REGISTER DATA CONTROL: SOFT RESET, SYNC, AND SINGLE-SHOT CONTROL REGISTER INTERFACE CONFIGURATION REGISTER DIGITAL FILTER RAM BUILT IN SELF TEST (BIST) REGISTER STATUS REGISTER REVISION IDENTIFICATION REGISTER GPIO CONTROL REGISTER GPIO WRITE DATA REGISTER GPIO READ DATA REGISTER ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 0 TO CHANNEL 3 ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 4 TO CHANNEL 7 POSITIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER NEGATIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER OFFSET REGISTERS GAIN REGISTERS SYNC PHASE OFFSET REGISTERS ADC DIAGNOSTIC RECEIVE SELECT REGISTER ADC DIAGNOSTIC CONTROL REGISTER MODULATOR DELAY CONTROL REGISTER CHOPPING CONTROL REGISTER AD7768-4 REGISTER MAP DETAILS (SPI CONTROL) AD7768-4 REGISTER MAP CHANNEL STANDBY REGISTER CHANNEL MODE A REGISTER CHANNEL MODE B REGISTER CHANNEL MODE SELECT REGISTER POWER MODE SELECT REGISTER GENERAL DEVICE CONFIGURATION REGISTER DATA CONTROL: SOFT RESET, SYNC, AND SINGLE-SHOT CONTROL REGISTER INTERFACE CONFIGURATION REGISTER DIGITAL FILTER RAM BUILT IN SELF TEST (BIST) REGISTER STATUS REGISTER REVISION IDENTIFICATION REGISTER GPIO CONTROL REGISTER GPIO WRITE DATA REGISTER GPIO READ DATA REGISTER ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 0 AND CHANNEL 1 ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 2 AND CHANNEL 3 POSITIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER NEGATIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER OFFSET REGISTERS GAIN REGISTERS SYNC PHASE OFFSET REGISTERS ADC DIAGNOSTIC RECEIVE SELECT REGISTER ADC DIAGNOSTIC CONTROL REGISTER MODULATOR DELAY CONTROL REGISTER CHOPPING CONTROL REGISTER OUTLINE DIMENSIONS ORDERING GUIDE