Datasheet AD7768, AD7768-4 (Analog Devices) - 2
| 制造商 | Analog Devices |
| 描述 | 4-Channel, 24-Bit, Simultaneous Sampling ADC, Power Scaling, 110.8 kHz BW |
| 页数 / 页 | 99 / 2 — AD7768/AD7768-4. Data Sheet. TABLE OF CONTENTS |
| 修订版 | B |
| 文件格式/大小 | PDF / 2.4 Mb |
| 文件语言 | 英语 |
AD7768/AD7768-4. Data Sheet. TABLE OF CONTENTS
该数据表的模型线
文件文字版本
link to page 1 link to page 1 link to page 1 link to page 3 link to page 5 link to page 6 link to page 12 link to page 16 link to page 17 link to page 21 link to page 21 link to page 21 link to page 22 link to page 30 link to page 40 link to page 41 link to page 41 link to page 42 link to page 44 link to page 45 link to page 46 link to page 46 link to page 49 link to page 50 link to page 53 link to page 54 link to page 54 link to page 55 link to page 56 link to page 56 link to page 56 link to page 56 link to page 58 link to page 58 link to page 59 link to page 61 link to page 61 link to page 62 link to page 71 link to page 71 link to page 72 link to page 72 link to page 74 link to page 74 link to page 75 link to page 75 link to page 76 link to page 76 link to page 77 link to page 77 link to page 78 link to page 78 link to page 79 link to page 79 link to page 79 link to page 80 link to page 80 link to page 80 link to page 80 link to page 81 link to page 81 link to page 81 link to page 82 link to page 82 link to page 83 link to page 83 link to page 83 link to page 84 link to page 85 link to page 85 link to page 86 link to page 86 link to page 88 link to page 88 link to page 89 link to page 89 link to page 89 link to page 90 link to page 91 link to page 91 link to page 91
AD7768/AD7768-4 Data Sheet TABLE OF CONTENTS
Features .. 1 AD7768 Register Map Details (SPI Control) .. 72 Applications ... 1 AD7768 Register Map.. 72 Functional Block Diagram .. 1 Channel Standby Register ... 74 Revision History ... 3 Channel Mode A Register ... 74 General Description ... 5 Channel Mode B Register ... 75 Specifications ... 6 Channel Mode Select Register .. 75 1.8 V IOVDD Specifications ... 12 Power Mode Select Register .. 76 Timing Specifications .. 16 General Device Configuration Register .. 76 1.8 V IOVDD Timing Specifications ... 17 Data Control: Soft Reset, Sync, and Single-Shot Control Absolute Maximum Ratings .. 21 Register .. 77 Thermal Resistance .. 21 Interface Configuration Register .. 78 ESD Caution .. 21 Digital Filter RAM Built In Self Test (BIST) Register.. 78 Pin Configurations and Function Descriptions ... 22 Status Register ... 79 Typical Performance Characteristics ... 30 Revision Identification Register ... 79 Terminology .. 40 GPIO Control Register .. 79 Theory of Operation .. 41 GPIO Write Data Register ... 80 Clocking, Sampling Tree, and Power Scaling ... 41 GPIO Read Data Register .. 80 Noise Performance and Resolution .. 42 Analog Input Precharge Buffer Enable Register Channel 0 to Channel 3 .. 80 Applications Information .. 44 Analog Input Precharge Buffer Enable Register Channel 4 to Power Supplies .. 45 Channel 7 .. 81 Device Configuration .. 46 Positive Reference Precharge Buffer Enable Register .. 81 Pin Control .. 46 Negative Reference Precharge Buffer Enable Register .. 82 SPI Control .. 49 Offset Registers ... 82 SPI Control Functionality ... 50 Gain Registers ... 83 SPI Control Mode Extra Diagnostic Features .. 53 Sync Phase Offset Registers .. 83 Circuit Information .. 54 ADC Diagnostic Receive Select Register .. 83 Core Signal Chain ... 54 ADC Diagnostic Control Register ... 84 Analog Inputs .. 55 Modulator Delay Control Register ... 85 VCM ... 56 Chopping Control Register ... 85 Reference Input ... 56 AD7768-4 Register Map Details (SPI Control) .. 86 Clock Selection ... 56 AD7768-4 Register Map .. 86 Digital Filtering ... 56 Channel Standby Register ... 88 Decimation Rate Control .. 58 Channel Mode A Register ... 88 Antialiasing ... 58 Channel Mode B Register ... 89 Calibration ... 59 Channel Mode Select Register .. 89 Data Interface .. 61 Power Mode Select Register .. 89 Setting the Format of Data Output .. 61 General Device Configuration Register .. 90 ADC Conversion Output: Header and Data .. 62 Data Control: Soft Reset, Sync, and Single-Shot Control Functionality ... 71 Register .. 91 GPIO Functionality .. 71 Interface Configuration Register .. 91 Rev. A | Page 2 of 99 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS 1.8 V IOVDD SPECIFICATIONS TIMING SPECIFICATIONS 1.8 V IOVDD TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CLOCKING, SAMPLING TREE, AND POWER SCALING Example of Power vs. Noise Performance Optimization Configuration A Configuration B Clocking Out the ADC Conversion Results (DCLK) NOISE PERFORMANCE AND RESOLUTION APPLICATIONS INFORMATION POWER SUPPLIES Recommended Power Supply Configuration 1.8 V IOVDD Operation Analog Supply Internal Connectivity DEVICE CONFIGURATION Interface Data Format PIN CONTROL Setting the Filter Setting the Decimation Rate Operating Mode Diagnostics Configuration Example Channel Standby SPI CONTROL Accessing the ADC Register Map SPI Interface Details SPI Control Interface Error Handling SPI Reset Configuration SPI CONTROL FUNCTIONALITY Channel Configuration Channel Modes Reset over SPI Control Interface Sleep Mode Channel Standby Clocking Selections MCLK Source Selection Interface Configuration CRC Protection ADC Synchronization over SPI Analog Input Precharge Buffers Reference Precharge Buffers Per Channel Calibration Gain, Offset, and Sync Phase GPIOs SPI CONTROL MODE EXTRA DIAGNOSTIC FEATURES RAM Built In Self Test Revision Identification Number Diagnostic Meter Mode CIRCUIT INFORMATION CORE SIGNAL CHAIN ADC Power Modes ANALOG INPUTS VCM REFERENCE INPUT CLOCK SELECTION DIGITAL FILTERING Sinc5 Filter Wideband Low Ripple Filter DECIMATION RATE CONTROL ANTIALIASING Modulator Sampling Frequency Modulator Chopping Frequency Modulator Saturation Point CALIBRATION Offset Adjustment Gain Adjustment Sync Phase Offset Adjustment DATA INTERFACE SETTING THE FORMAT OF DATA OUTPUT ADC CONVERSION OUTPUT: HEADER AND DATA Chip Error Filter Not Settled Repeated Data Filter Type Filter Saturated Channel ID Data Interface: Standard Conversion Operation Data Interface: One-Shot Conversion Operation Daisy-Chaining Synchronization CRC Check on Data Interface FUNCTIONALITY GPIO FUNCTIONALITY AD7768 REGISTER MAP DETAILS (SPI CONTROL) AD7768 REGISTER MAP CHANNEL STANDBY REGISTER CHANNEL MODE A REGISTER CHANNEL MODE B REGISTER CHANNEL MODE SELECT REGISTER POWER MODE SELECT REGISTER GENERAL DEVICE CONFIGURATION REGISTER DATA CONTROL: SOFT RESET, SYNC, AND SINGLE-SHOT CONTROL REGISTER INTERFACE CONFIGURATION REGISTER DIGITAL FILTER RAM BUILT IN SELF TEST (BIST) REGISTER STATUS REGISTER REVISION IDENTIFICATION REGISTER GPIO CONTROL REGISTER GPIO WRITE DATA REGISTER GPIO READ DATA REGISTER ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 0 TO CHANNEL 3 ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 4 TO CHANNEL 7 POSITIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER NEGATIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER OFFSET REGISTERS GAIN REGISTERS SYNC PHASE OFFSET REGISTERS ADC DIAGNOSTIC RECEIVE SELECT REGISTER ADC DIAGNOSTIC CONTROL REGISTER MODULATOR DELAY CONTROL REGISTER CHOPPING CONTROL REGISTER AD7768-4 REGISTER MAP DETAILS (SPI CONTROL) AD7768-4 REGISTER MAP CHANNEL STANDBY REGISTER CHANNEL MODE A REGISTER CHANNEL MODE B REGISTER CHANNEL MODE SELECT REGISTER POWER MODE SELECT REGISTER GENERAL DEVICE CONFIGURATION REGISTER DATA CONTROL: SOFT RESET, SYNC, AND SINGLE-SHOT CONTROL REGISTER INTERFACE CONFIGURATION REGISTER DIGITAL FILTER RAM BUILT IN SELF TEST (BIST) REGISTER STATUS REGISTER REVISION IDENTIFICATION REGISTER GPIO CONTROL REGISTER GPIO WRITE DATA REGISTER GPIO READ DATA REGISTER ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 0 AND CHANNEL 1 ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 2 AND CHANNEL 3 POSITIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER NEGATIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER OFFSET REGISTERS GAIN REGISTERS SYNC PHASE OFFSET REGISTERS ADC DIAGNOSTIC RECEIVE SELECT REGISTER ADC DIAGNOSTIC CONTROL REGISTER MODULATOR DELAY CONTROL REGISTER CHOPPING CONTROL REGISTER OUTLINE DIMENSIONS ORDERING GUIDE
AD7768/AD7768-4 Data Sheet TABLE OF CONTENTS
Features .. 1 AD7768 Register Map Details (SPI Control) .. 72 Applications ... 1 AD7768 Register Map.. 72 Functional Block Diagram .. 1 Channel Standby Register ... 74 Revision History ... 3 Channel Mode A Register ... 74 General Description ... 5 Channel Mode B Register ... 75 Specifications ... 6 Channel Mode Select Register .. 75 1.8 V IOVDD Specifications ... 12 Power Mode Select Register .. 76 Timing Specifications .. 16 General Device Configuration Register .. 76 1.8 V IOVDD Timing Specifications ... 17 Data Control: Soft Reset, Sync, and Single-Shot Control Absolute Maximum Ratings .. 21 Register .. 77 Thermal Resistance .. 21 Interface Configuration Register .. 78 ESD Caution .. 21 Digital Filter RAM Built In Self Test (BIST) Register.. 78 Pin Configurations and Function Descriptions ... 22 Status Register ... 79 Typical Performance Characteristics ... 30 Revision Identification Register ... 79 Terminology .. 40 GPIO Control Register .. 79 Theory of Operation .. 41 GPIO Write Data Register ... 80 Clocking, Sampling Tree, and Power Scaling ... 41 GPIO Read Data Register .. 80 Noise Performance and Resolution .. 42 Analog Input Precharge Buffer Enable Register Channel 0 to Channel 3 .. 80 Applications Information .. 44 Analog Input Precharge Buffer Enable Register Channel 4 to Power Supplies .. 45 Channel 7 .. 81 Device Configuration .. 46 Positive Reference Precharge Buffer Enable Register .. 81 Pin Control .. 46 Negative Reference Precharge Buffer Enable Register .. 82 SPI Control .. 49 Offset Registers ... 82 SPI Control Functionality ... 50 Gain Registers ... 83 SPI Control Mode Extra Diagnostic Features .. 53 Sync Phase Offset Registers .. 83 Circuit Information .. 54 ADC Diagnostic Receive Select Register .. 83 Core Signal Chain ... 54 ADC Diagnostic Control Register ... 84 Analog Inputs .. 55 Modulator Delay Control Register ... 85 VCM ... 56 Chopping Control Register ... 85 Reference Input ... 56 AD7768-4 Register Map Details (SPI Control) .. 86 Clock Selection ... 56 AD7768-4 Register Map .. 86 Digital Filtering ... 56 Channel Standby Register ... 88 Decimation Rate Control .. 58 Channel Mode A Register ... 88 Antialiasing ... 58 Channel Mode B Register ... 89 Calibration ... 59 Channel Mode Select Register .. 89 Data Interface .. 61 Power Mode Select Register .. 89 Setting the Format of Data Output .. 61 General Device Configuration Register .. 90 ADC Conversion Output: Header and Data .. 62 Data Control: Soft Reset, Sync, and Single-Shot Control Functionality ... 71 Register .. 91 GPIO Functionality .. 71 Interface Configuration Register .. 91 Rev. A | Page 2 of 99 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS 1.8 V IOVDD SPECIFICATIONS TIMING SPECIFICATIONS 1.8 V IOVDD TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CLOCKING, SAMPLING TREE, AND POWER SCALING Example of Power vs. Noise Performance Optimization Configuration A Configuration B Clocking Out the ADC Conversion Results (DCLK) NOISE PERFORMANCE AND RESOLUTION APPLICATIONS INFORMATION POWER SUPPLIES Recommended Power Supply Configuration 1.8 V IOVDD Operation Analog Supply Internal Connectivity DEVICE CONFIGURATION Interface Data Format PIN CONTROL Setting the Filter Setting the Decimation Rate Operating Mode Diagnostics Configuration Example Channel Standby SPI CONTROL Accessing the ADC Register Map SPI Interface Details SPI Control Interface Error Handling SPI Reset Configuration SPI CONTROL FUNCTIONALITY Channel Configuration Channel Modes Reset over SPI Control Interface Sleep Mode Channel Standby Clocking Selections MCLK Source Selection Interface Configuration CRC Protection ADC Synchronization over SPI Analog Input Precharge Buffers Reference Precharge Buffers Per Channel Calibration Gain, Offset, and Sync Phase GPIOs SPI CONTROL MODE EXTRA DIAGNOSTIC FEATURES RAM Built In Self Test Revision Identification Number Diagnostic Meter Mode CIRCUIT INFORMATION CORE SIGNAL CHAIN ADC Power Modes ANALOG INPUTS VCM REFERENCE INPUT CLOCK SELECTION DIGITAL FILTERING Sinc5 Filter Wideband Low Ripple Filter DECIMATION RATE CONTROL ANTIALIASING Modulator Sampling Frequency Modulator Chopping Frequency Modulator Saturation Point CALIBRATION Offset Adjustment Gain Adjustment Sync Phase Offset Adjustment DATA INTERFACE SETTING THE FORMAT OF DATA OUTPUT ADC CONVERSION OUTPUT: HEADER AND DATA Chip Error Filter Not Settled Repeated Data Filter Type Filter Saturated Channel ID Data Interface: Standard Conversion Operation Data Interface: One-Shot Conversion Operation Daisy-Chaining Synchronization CRC Check on Data Interface FUNCTIONALITY GPIO FUNCTIONALITY AD7768 REGISTER MAP DETAILS (SPI CONTROL) AD7768 REGISTER MAP CHANNEL STANDBY REGISTER CHANNEL MODE A REGISTER CHANNEL MODE B REGISTER CHANNEL MODE SELECT REGISTER POWER MODE SELECT REGISTER GENERAL DEVICE CONFIGURATION REGISTER DATA CONTROL: SOFT RESET, SYNC, AND SINGLE-SHOT CONTROL REGISTER INTERFACE CONFIGURATION REGISTER DIGITAL FILTER RAM BUILT IN SELF TEST (BIST) REGISTER STATUS REGISTER REVISION IDENTIFICATION REGISTER GPIO CONTROL REGISTER GPIO WRITE DATA REGISTER GPIO READ DATA REGISTER ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 0 TO CHANNEL 3 ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 4 TO CHANNEL 7 POSITIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER NEGATIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER OFFSET REGISTERS GAIN REGISTERS SYNC PHASE OFFSET REGISTERS ADC DIAGNOSTIC RECEIVE SELECT REGISTER ADC DIAGNOSTIC CONTROL REGISTER MODULATOR DELAY CONTROL REGISTER CHOPPING CONTROL REGISTER AD7768-4 REGISTER MAP DETAILS (SPI CONTROL) AD7768-4 REGISTER MAP CHANNEL STANDBY REGISTER CHANNEL MODE A REGISTER CHANNEL MODE B REGISTER CHANNEL MODE SELECT REGISTER POWER MODE SELECT REGISTER GENERAL DEVICE CONFIGURATION REGISTER DATA CONTROL: SOFT RESET, SYNC, AND SINGLE-SHOT CONTROL REGISTER INTERFACE CONFIGURATION REGISTER DIGITAL FILTER RAM BUILT IN SELF TEST (BIST) REGISTER STATUS REGISTER REVISION IDENTIFICATION REGISTER GPIO CONTROL REGISTER GPIO WRITE DATA REGISTER GPIO READ DATA REGISTER ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 0 AND CHANNEL 1 ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 2 AND CHANNEL 3 POSITIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER NEGATIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER OFFSET REGISTERS GAIN REGISTERS SYNC PHASE OFFSET REGISTERS ADC DIAGNOSTIC RECEIVE SELECT REGISTER ADC DIAGNOSTIC CONTROL REGISTER MODULATOR DELAY CONTROL REGISTER CHOPPING CONTROL REGISTER OUTLINE DIMENSIONS ORDERING GUIDE