Datasheet AD7761 (Analog Devices) - 6

link to page 11 link to page 41 link to page 11 link to page 11 link to page 11 link to page 11 link to page 11 link to page 11 link to page 11 link to page 11
Data Sheet AD7761 SPECIFICATIONS
AVDD1A = AVDD1B = 4.5 V to 5.5 V, AVDD2A = AVDD2B = 2.0 V to 5.5 V, IOVDD = 1.72 V to 1.88 V and 2.25 V to 3.6 V, AVSS = DGND = 0 V, REFx+ = 4.096 V and REFx− = 0 V, MCLK = 32.768 MHz, analog input precharge buffers on, reference precharge buffers off, wideband filter, fCHOP = fMOD/32, TA = −40°C to +105°C, unless otherwise noted.
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit
ADC SPEED AND PERFORMANCE Output Data Rate (ODR), per Fast 8 256 kSPS Channel1 Median 4 128 kSPS Low power 1 32 kSPS −3 dB Bandwidth (BW) Fast, wideband filter 110.8 kHz Median, wideband filter 55.4 kHz Low power, wideband filter 13.8 kHz Data Output Coding Twos complement, MSB first No Missing Codes2 16 Bits DYNAMIC PERFORMANCE Decimation by 32, 256 kSPS ODR Dynamic Range Shorted input, wideband filter 97.3 97.7 dB Signal-to-Noise Ratio (SNR) 1 kHz, −0.5 dBFS, sine wave input Sinc5 filter 97.3 97.9 dB Wideband filter 97.3 97.7 dB Signal-to-Noise-and-Distortion 1 kHz, −0.5 dBFS, sine wave input 97.3 97.7 dB Ratio (SINAD) Total Harmonic Distortion (THD) 1 kHz, −0.5 dBFS, sine wave input −120 −107 dB Spurious-Free Dynamic Range (SFDR) 126 dBc INTERMODULATON DISTORTION (IMD) fINA = 9.7 kHz, fINB = 10.3 kHz Second order −125 dB Third order −124 dB ACCURACY INL3 Endpoint method ±1 ± 1.5 LSB Offset Error4 ±1 ±2 LSB Gain Error4 TA = 25°C ±5 ±40 LSB Gain Drift vs. Temperature2 ±0.01 ±0.02 LSB/°C VCM PIN Output With respect to AVSS (AVDD1 − V AVSS)/2 Load Regulation ∆VOUT/∆IL 400 µV/mA Voltage Regulation Applies to the following VCM output 5 µV/V options only: VCM = ∆VOUT/∆(AVDD1 − AVSS)/2, VCM = 1.65 V, and VCM = 2.5 V Short-Circuit Current 30 mA ANALOG INPUTS See the Analog Inputs section Differential Input Voltage Range VREF = (REFx+) − (REFx−) −VREF +VREF V Input Common-Mode Range2 AVSS AVDD1 V Absolute Analog Input Voltage Limits2 AVSS AVDD1 V Analog Input Current Unbuffered Differential component ±48 µA/V Common-mode component ±17 µA/V Precharge Buffer On5 −20 µA Input Current Drift Unbuffered ±5 nA/V/°C Precharge Buffer On ±31 nA/°C Rev. A | Page 5 of 75 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS TIMING SPECIFICATIONS 1.8 V IOVDD TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CLOCKING, SAMPLING TREE, AND POWER SCALING Example of Power vs. Noise Performance Optimization Configuration A Configuration B Clocking Out the ADC Conversion Results (DCLK) NOISE PERFORMANCE AND RESOLUTION APPLICATIONS INFORMATION POWER SUPPLIES Recommended Power Supply Configuration 1.8 V IOVDD Operation Analog Supply Internal Connectivity DEVICE CONFIGURATION Interface Data Format PIN CONTROL MODE Setting the Filter Setting the Decimation Rate Operating Mode Diagnostics Configuration Example Channel Standby SPI CONTROL Accessing the ADC Register Map SPI Interface Details SPI Control Interface Error Handling SPI Reset Configuration SPI CONTROL FUNCTIONALITY Channel Configuration Channel Modes Reset over SPI Control Interface Sleep Mode Channel Standby Mode Clocking Selections MCLK Source Selection Interface Configuration CRC Protection ADC Synchronization over SPI Analog Input Precharge Buffers Reference Precharge Buffers Per Channel Calibration Gain, Offset, and Sync Phase GPIOs SPI CONTROL MODE EXTRA DIAGNOSTIC FEATURES RAM Built In Self Test Revision Identification Number Diagnostic Meter Mode CIRCUIT INFORMATION CORE SIGNAL CHAIN ADC Power Modes ANALOG INPUTS VCM REFERENCE INPUT CLOCK SELECTION DIGITAL FILTERING Sinc5 Filter Wideband Low Ripple Filter Filter Settling Time DECIMATION RATE CONTROL ANTIALIASING Modulator Sampling Frequency Modulator Chopping Frequency Modulator Saturation Point CALIBRATION Offset Adjustment Gain Adjustment Sync Phase Offset Adjustment DATA INTERFACE SETTING THE FORMAT OF DATA OUTPUT ADC CONVERSION OUTPUT: HEADER AND DATA ERROR_FLAGGED Filter Not Settled Repeated Data Filter Type Filter Saturated Channel ID Data Interface: Standard Conversion Operation Data Interface: One-Shot Conversion Operation Daisy-Chaining Synchronization CRC Check on Data Interface CRC Code Example FUNCTIONALITY GPIO FUNCTIONALITY REGISTER MAP DETAILS (SPI CONTROL) REGISTER MAP CHANNEL STANDBY REGISTER CHANNEL MODE A REGISTER CHANNEL MODE B REGISTER CHANNEL MODE SELECT REGISTER POWER MODE SELECT REGISTER GENERAL DEVICE CONFIGURATION REGISTER DATA CONTROL: SOFT RESET, SYNC, AND SINGLE-SHOT CONTROL REGISTER INTERFACE CONFIGURATION REGISTER DIGITAL FILTER RAM BUILT IN SELF TEST (BIST) REGISTER STATUS REGISTER REVISION IDENTIFICATION REGISTER GPIO CONTROL REGISTER GPIO WRITE DATA REGISTER GPIO READ DATA REGISTER ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 0 TO CHANNEL 3 ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 4 TO CHANNEL 7 POSITIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER NEGATIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER OFFSET REGISTERS GAIN REGISTERS SYNC PHASE OFFSET REGISTERS ADC DIAGNOSTIC RECEIVE SELECT REGISTER ADC DIAGNOSTIC CONTROL REGISTER MODULATOR DELAY CONTROL REGISTER CHOPPING CONTROL REGISTER OUTLINE DIMENSIONS ORDERING GUIDE