Data SheetAD9684APERTURE DELAYNN + 35N + 36N + 39N + 40N – 1VIN±xN + xN + 37N + yN + 38N + 41SYNCHRONOUS LOW TO HIGH TRANSITIONS OF THE SYNC SIGNAL CAPTURED ON THE RISING EDGE OF THE CLK SIGNAL CAUSES THE DCO INTERNAL DIVIDER TO BE RESETSYNC+SYNC–CLK+CLK–tCLKFIXED DELAY FROM SYNC EVENT TO DCO KNOWN PHASECONSTANT LATENCY = X CLK CYCLEStDCOtPDDCO± (DATA CLOCK OUTPUT)0° PHASE ADJUSTDCO± (DATA CLOCK OUTPUT)90° PHASE ADJUST1DCO± (DATA CLOCK OUTPUT)180° PHASE ADJUSTDCO± (DATA CLOCK OUTPUT)270° PHASE ADJUST2tSKEWRtSKEWFCONVERTER 0CONVERTER 0CONVERTER 0CONVERTER 0CONVERTER 0SAMPLESAMPLESAMPLESAMPLESAMPLE[N][N + 1][N + 2][N + 3][N + 4]STATUS+(OVERRANGE/STATUS BIT)STATUSSTATUSSTATUSSTATUSSTATUSSTATUSSTATUSSTATUS–D13±D13D13D13D13D13D13D13D0±D0D0D0D0D0D0D0 004 190° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±. 2270° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±. 13015- Figure 4. Parallel Interleaved Mode—One Converter, ≤14-Bit Data Rev. 0 | Page 9 of 64 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Analog Input Controls and SFDR Optimization Absolute Maximum Input Swing VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider Input Clock Divider ½ Period Delay Adjustment Clock Fine Delay Adjustment Clock Jitter Considerations POWER-DOWN/STANDBY MODE TEMPERATURE DIODE ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A AND FD_B) SIGNAL MONITOR DIGITAL DOWNCONVERTERS (DDCs) DDC I/Q INPUT SELECTION DDC I/Q OUTPUT SELECTION DDC GENERAL DESCRIPTION FREQUENCY TRANSLATION GENERAL DESCRIPTION Variable IF Mode 0 Hz IF (ZIF) Mode fS/4 Hz IF Mode Test Mode DDC NCO PLUS MIXER LOSS AND SFDR NUMERICALLY CONTROLLED OSCILLATOR Setting Up the NCO FTW and POW NCO Synchronization Mixer FIR FILTERS GENERAL DESCRIPTION HALF-BAND FILTERS HB4 Filter HB3 Filter HB2 Filter HB1 Filter DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION BLOCK DDC EXAMPLE CONFIGURATIONS DIGITAL OUTPUTS DIGITAL OUTPUTS Timing Data Clock Output ADC OVERRANGE MULTICHIP SYNCHRONIZATION SYNC± SETUP AND HOLD WINDOW MONITOR TEST MODES ADC TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Unassigned and Reserved Locations Default Values Logic Levels Channel-Specific Registers SPI Soft Reset MEMORY MAP REGISTER TABLE APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS OUTLINE DIMENSIONS ORDERING GUIDE