Datasheet AD9652 (Analog Devices) - 5

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AD9652 Data Sheet ADC AC SPECIFICATIONS
AVDD3 = 3.3 V, AVDD = AVDD_CLK = 1.8 V, SPIVDD = DRVDD = 1.8 V, sample rate = 310 MSPS (clock input = 1240 MHz, AD9652 divided by 4), VIN = −1.0 dBFS differential input, 2.5 V p-p full-scale input range, DCS enabled, dither disabled, unless otherwise noted.
Table 2. VREF = 1 V VREF = 1.25 V, Default Parameter1 Temperature Min Typ Max Min Typ Max Unit
DIFFERENTIAL INPUT VOLTAGE 25°C 2.0 2.5 V p-p SIGNAL-TO-NOISE RATIO (SNR) fIN = 30 MHz (Use Nyquist 1 Settings) 25°C 74.0 75.4 dBFS fIN = 70 MHz (Use Nyquist 1 Settings) 25°C 73.6 74.0 75.0 dBFS Full 73.3 dBFS fIN = 70 MHz (Use Nyquist 1 Settings, with Dither Enabled) 25°C 73.1 74.3 dBFS fIN = 170 MHz (Use Nyquist 2 Settings) 25°C 72.1 73.7 dBFS fIN = 170 MHz (Use Nyquist 2 Settings, with Dither Enabled) 25°C 71.2 72.0 dBFS fIN = 305 MHz (Use Nyquist 2 Settings) 25°C 70.1 70.7 dBFS fIN = 400 MHz (Use Nyquist 3 Settings) 25°C 67.9 68.0 dBFS SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 30 MHz (Use Nyquist 1 Settings) 25°C 72.8 74.2 dBFS fIN = 70 MHz (Use Nyquist 1 Settings) 25°C 73.5 73.8 74.6 dBFS Full 73.2 dBFS fIN = 70 MHz (Use Nyquist 1 Settings, with Dither Enabled) 25°C 73.0 74.0 dBFS fIN = 170 MHz (Use Nyquist 2 Settings) 25°C 72.0 72.6 dBFS fIN = 170 MHz (Use Nyquist 2 Settings, with Dither Enabled) 25°C 71.1 71.7 dBFS fIN = 305 MHz (Use Nyquist 2 Settings) 25°C 68.5 dBFS fIN = 400 MHz (Use Nyquist 3 Settings) 25°C 65.8 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 30 MHz (Use Nyquist 1 Settings) 25°C 11.8 12.0 Bits fIN = 70 MHz (Use Nyquist 1 Settings) 25°C 12 12.0 12.1 Bits Full 11.9 Bits fIN = 70 MHz (Use Nyquist 1 Settings, with Dither Enabled) 25°C 11.8 12.0 Bits fIN = 170 MHz (Use Nyquist 2 Settings) 25°C 11.7 11.8 Bits fIN = 170 MHz (Use Nyquist 2 Settings, with Dither Enabled) 25°C 11.5 11.6 Bits fIN = 305 MHz (Use Nyquist 2 Settings) 25°C 11.1 Bits fIN = 400 MHz (Use Nyquist 3 Settings) 25°C 10.6 Bits WORST SECOND OR THIRD HARMONIC fIN = 30 MHz (Use Nyquist 1 Settings) 25°C −96 −94 dBc fIN = 70 MHz (Use Nyquist 1 Settings) 25°C −90 −87 −83 dBc Full −83 dBc fIN = 70 MHz (Use Nyquist 1 Settings, with Dither Enabled) 25°C −92 −89 dBc fIN = 170 MHz (Use Nyquist 2 Settings) 25°C −87 −85 dBc fIN = 170 MHz (Use Nyquist 2 Settings, with Dither Enabled) 25°C −87 −85 dBc fIN = 305 MHz (Use Nyquist 2 Settings) 25°C −89 −86 dBc fIN = 400 MHz (Use Nyquist 3 Settings) 25°C −80 −77 dBc SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 30 MHz (Use Nyquist 1 Settings) 25°C 96 94 dBc fIN = 70 MHz (Use Nyquist 1 Settings) 25°C 90 83 87 dBc Full 83 dBc fIN = 70 MHz (Use Nyquist 1 Settings. with Dither Enabled) 25°C 92 89 dBc fIN = 170 MHz (Use Nyquist 2 Settings) 25°C 84 85 dBc fIN = 170 MHz (Use Nyquist 2 Settings, with Dither Enabled) 25°C 87 85 dBc fIN = 305 MHz (Use Nyquist 2 Settings) 25°C 89 86 dBc fIN = 400 MHz (Use Nyquist 3 Settings) 25°C 80 77 dBc Rev. B | Page 4 of 36 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Revision History Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Common-Mode Voltage Servo Dither Large Signal Fast Fourier Transform Small Signal FFT Static Linearity Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Standby Mode Internal Background Calibration Digital Outputs Timing Data Clock Output ADC Overrange Fast Threshold Detection (FDA/FDB) Serial Port Interface Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open and Reserved Locations Default Values Logic Levels Transfer Register Map Channel Specific Registers Memory Map Register Table Applications Information Design Guidelines Power and Ground Recommendations VCM RBIAS Reference Decoupling SPI Port Outline Dimensions Ordering Guide