Datasheet AD9652 (Analog Devices) - 10

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Data Sheet AD9652 ABSOLUTE MAXIMUM RATINGS Table 6. THERMAL CHARACTERISTICS Parameter Rating
Typical θJA is specified for both a 4-layer printed circuit board Electrical (PCB) with a solid ground plane from the JEDEC 51-2 and an AVDD3 to AGND −0.3 V to +3.6 V 8-layer PCB. The 8-layer PCB has 2 oz copper layers (M1 and AVDD_CLK to AGND −0.3 V to +2.0 V M8), 1 oz copper inner layers, and vias connecting to layers M2, AVDD to AGND −0.3 V to +2.0 V M5, and M7. DRVDD to AGND −0.3 V to +2.0 V As shown in Table 7, airflow increases heat dissipation, which SPIVDD to AGND −0.3 V to +3.6 V reduces θJA. In addition, metal in direct contact with the VIN+A/VIN+B, VIN−A/VIN−B to AGND 1.2 V to 3.0 V package leads from metal traces, through holes, ground, and CLK+, CLK− to AGND −0.3 V to AVDD_CLK + power planes, reduces the θJA. 0.2 V SYNC to AGND −0.3 V to AVDD_CLK +
Table 7. Thermal Resistance
0.2 V
Airflow
VCM to AGND −0.3 V to AVDD + 0.2 V
Velocity
CSB to AGND −0.3 V to SPIVDD + 0.3 V
Package Type (m/sec) Board Type θ 2 JA Unit
SCLK to AGND −0.3 V to SPIVDD + 0.3 V 144-Ball CSP_BGA 0 8-layer PCB 15.8 °C/W SDIO to AGND −0.3 V to SPIVDD + 0.3 V 10 mm × 10 mm 1.0 8-layer PCB 13.9 °C/W PDWN to AGND −0.3 V to DRVDD + 0.3 V (BC-144-6) 0 JEDEC1 21.7 °C/W OR+/OR− to AGND −0.3 V to DRVDD + 0.3 V 1.0 JEDEC1 19.2 °C/W D0± Through D15± to AGND −0.3 V to DRVDD + 0.3 V 1 Per JEDEC JESD51-7, plus JEDEC 25-5 2S2P test board. DCO± to AGND −0.3 V to DRVDD + 0.3 V 2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). Environmental Operating Temperature Range −40°C to +85°C (Ambient)
ESD CAUTION
Maximum Junction Temperature 125°C Under Bias Storage Temperature Range −65°C to +150°C (Ambient) Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. B | Page 9 of 36 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Revision History Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Common-Mode Voltage Servo Dither Large Signal Fast Fourier Transform Small Signal FFT Static Linearity Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Standby Mode Internal Background Calibration Digital Outputs Timing Data Clock Output ADC Overrange Fast Threshold Detection (FDA/FDB) Serial Port Interface Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open and Reserved Locations Default Values Logic Levels Transfer Register Map Channel Specific Registers Memory Map Register Table Applications Information Design Guidelines Power and Ground Recommendations VCM RBIAS Reference Decoupling SPI Port Outline Dimensions Ordering Guide