Datasheet ADAS3022 (Analog Devices) - 9

ADAS3022 Data Sheet t t ACQ CYC SOC EOC SOC EOC t t POWER DDC QUIET tDAC UP NOTE 1 NOTE 2 NOTE 1 CONVERSION (n – 1) ACQUISITION (n) CONVERSION (n) ACQUISITION (n + 1) PHASE CONVERSION (n + 1) UNDEFINED UNDEFINED UNDEFINED UNDEFINED UNDEFINED CNV BUSY t NOTE 5 DDCA NOTE 2 tAD NOTE 4 CS X 1 16/32 1 16 SCK NOTE 3 CFG DIN CFG (n + 2) CFG (n + 2) CFG (n + 3) CFG (n + 3) INVALID DATA DATA (n – 1) DATA (n – 1) DATA (n) DATA (n) SDO INVALID INVALID INVALID INVALID INVALID EOC EOC EOC ACQUISITION CONVERSION ACQUISITION CONVERSION ACQUISITION CONVERSION PHASE (n + 2) (n + 2) (n + 3) (n + 3) (n + 4) (n + 4) CNV BUSY CS 1 16 1 16 1 SCK DIN CFG (n + 4) CFG (n + 4) CFG (n + 5) CFG (n + 5) CFG (n + 6) CFG (n + 6) DATA (n + 1) SDO DATA (n + 1) DATA (n + 2) DATA (n + 2) DATA (n + 3) DATA (n + 3) INVALID INVALID NOTES 1. DATA ACCESS CAN OCCUR DURING A CONVERSION ( tDDC), AFTER A CONVERSION (tDAC), OR BOTH DURING AND AFTER A CONVERSION. THE CONVERSION RESULT AND THE CFG REGISTER ARE UPDATED AT THE END OF A CONVERSION (EOC). 2. DATA ACCESS CAN ALSO OCCUR UP TO tDDCA WHILE BUSY IS ACTIVE (SEE THE DIGITAL INTERFACE SECTION FOR DETAILS). ALL OF THE BUSY TIME CAN BE USED TO ACQUIRE DATA. 3. A TOTAL OF 16 SCK FALLING EDGES IS REQUIRED FOR A CONVERSION RESULT. AN ADDITIONAL 16 EDGES ARE REQUIRED TO READ BACK THE CFG RESULT ASSOCIATED WITH THE CURRENT CONVERSION. 4. CS CAN BE HELD LOW OR CONNECTED TO CNV. CS WITH FULL INDEPENDENT CONTROL IS SHOWN IN THIS FIGURE. 5. FOR OPTIMAL PERFORMANCE, DATA ACCESS SHOULD NOT OCCUR DURING THE SAMPLING EDGE. A MINIMUM TIME
028
OF THE APERTURE DELAY (tAD) SHOULD ELAPSE PRIOR TO DATA ACCESS.
10516- Figure 4. General Timing Diagram Rev. C | Page 8 of 40 Document Outline Features Applications General Description Functional Block Diagram Table of Contents Revision History Specifications Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Overview ADAS3022 Operation Transfer Function Typical Application Connection Diagram Analog Inputs Input Structure Programmable Gain Common-Mode Operating Range Fully Differential, Antiphase Signals with a Zero Common Mode Fully Differential, Antiphase Signals with a Nonzero Common Mode Differential, Nonantiphase Signals with a Zero Common Mode Single-Ended Signals with a Nonzero DC Offset (Asymmetrical) Single-Ended Signals with a 0 V DC Offset (Symmetrical) Multiplexer Channel Sequencer Auxiliary Input Channel Driver Amplifier Choice Voltage Reference Output/Input Internal Reference External Reference and Internal Buffer External Reference Reference Decoupling Power Supply Core Supplies High Voltage Supplies Power Dissipation Modes Fully Operational Mode Power-Down Mode Conversion Modes Warp Mode (CMS = 0) Normal Mode (CMS = 1, Default) Digital Interface Conversion Control CNV Rising Edge—Start of a Conversion (SOC) BUSY Falling Edge—End of a Conversion (EOC) Reset and Power-Down (PD) Inputs Serial Data Interface CPHA Sampling on the SCK Falling Edge Sampling on the SCK Rising Edge (Alternate Edge) CFG Readback General Considerations Data Access During Conversion—Maximum Throughput General Timing Configuration Register On Demand Conversion Mode Channel Sequencer Details INx and COM Inputs (MUX = 1, TEMPB = 1) INx and COM Inputs with AUX Inputs (MUX = 0, TEMPB = 1) INx and COM Inputs with Temperature Sensor (MUX = 1, TEMPB = 0) INx and COM Inputs with AUX Inputs and Temperature Sensor (MUX = 0, TEMPB = 0) Sequencer Modes Basic Sequencer Mode (SEQ = 11) Update During Sequence (SEQ = 01) Advanced Sequencer Mode (SEQ = 10) Outline Dimensions Ordering Guide