Datasheet AD9250 (Analog Devices) - 2
| 制造商 | Analog Devices |
| 描述 | 14-Bit, 170 MSPS/250 MSPS, JESD204B, Dual Analog-to-Digital Converter |
| 页数 / 页 | 45 / 2 — AD9250. Data Sheet. TABLE OF CONTENTS |
| 修订版 | E |
| 文件格式/大小 | PDF / 1.5 Mb |
| 文件语言 | 英语 |
AD9250. Data Sheet. TABLE OF CONTENTS
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AD9250 Data Sheet TABLE OF CONTENTS
Features .. 1 JESD204B Overview .. 25 Applications ... 1 JESD204B Synchronization Details ... 26 Functional Block Diagram .. 1 Link Setup Parameters ... 26 Product Highlights ... 1 Frame and Lane Alignment Monitoring and Correction ... 30 Revision History ... 3 Digital Outputs and Timing ... 30 General Description ... 4 ADC Overrange and Gain Control .. 32 Specifications ... 5 ADC Overrange (OR) .. 32 ADC DC Specifications ... 5 Gain Switching .. 32 ADC AC Specifications ... 6 DC Correction .. 33 Digital Specifications ... 7 DC Correction Bandwidth .. 33 Switching Specifications .. 9 DC Correction Readback .. 33 Timing Specifications .. 10 DC Correction Freeze .. 33 Absolute Maximum Ratings .. 11 DC Correction (DCC) Enable Bits .. 33 Thermal Characteristics .. 11 Serial Port Interface (SPI) .. 34 ESD Caution .. 11 Configuration Using the SPI ... 34 Pin Configuration and Function Descriptions ... 12 Hardware Interface ... 34 Typical Performance Characteristics ... 14 SPI Accessible Features .. 35 Equivalent Circuits ... 18 Memory Map .. 36 Theory of Operation .. 20 Reading the Memory Map Register Table ... 36 ADC Architecture .. 20 Memory Map Register Table ... 37 Analog Input Considerations .. 20 Memory Map Register Description ... 41 Voltage Reference ... 21 Applications Information .. 42 Clock Input Considerations .. 21 Design Guidelines .. 42 Power Dissipation and Standby Mode ... 24 SPI Initialization Sequence ... 42 Digital Outputs ... 25 Outline Dimensions ... 45 JESD204B Transmit Top Level Description .. 25 Ordering Guide .. 45 Rev. E | Page 2 of 45 Document Outline Features Applications Functional Block Diagram Product Highlights Revision History General Description Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Clock Input Considerations Nyquist Clock Input Options RF Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Standby Mode Digital Outputs JESD204B Transmit Top Level Description JESD204B Overview JESD204B Synchronization Details CGS Phase ILAS Phase Data Transmission Phase Link Setup Parameters Disable Lanes Before Changing Configuration Select Quick Configuration Option Configure Detailed Options Check FCHK, Checksum of JESD204B Interface Parameters Additional Digital Output Configuration Options Re-Enable Lanes After Configuration Internal FIFO Timing Optimization Frame and Lane Alignment Monitoring and Correction Digital Outputs and Timing ADC Overrange and Gain Control ADC Overrange (OR) Gain Switching Fast Threshold Detection (FDA and FDB) DC Correction DC Correction Bandwidth DC Correction Readback DC Correction Freeze DC Correction (DCC) Enable Bits Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface SPI Accessible Features Memory Map Reading the Memory Map Register Table Open and Reserved Locations Default Values Logic Levels Channel-Specific Registers Memory Map Register Table Memory Map Register Description Applications Information Design Guidelines Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations VCM SPI Port SPI Initialization Sequence Outline Dimensions Ordering Guide
AD9250 Data Sheet TABLE OF CONTENTS
Features .. 1 JESD204B Overview .. 25 Applications ... 1 JESD204B Synchronization Details ... 26 Functional Block Diagram .. 1 Link Setup Parameters ... 26 Product Highlights ... 1 Frame and Lane Alignment Monitoring and Correction ... 30 Revision History ... 3 Digital Outputs and Timing ... 30 General Description ... 4 ADC Overrange and Gain Control .. 32 Specifications ... 5 ADC Overrange (OR) .. 32 ADC DC Specifications ... 5 Gain Switching .. 32 ADC AC Specifications ... 6 DC Correction .. 33 Digital Specifications ... 7 DC Correction Bandwidth .. 33 Switching Specifications .. 9 DC Correction Readback .. 33 Timing Specifications .. 10 DC Correction Freeze .. 33 Absolute Maximum Ratings .. 11 DC Correction (DCC) Enable Bits .. 33 Thermal Characteristics .. 11 Serial Port Interface (SPI) .. 34 ESD Caution .. 11 Configuration Using the SPI ... 34 Pin Configuration and Function Descriptions ... 12 Hardware Interface ... 34 Typical Performance Characteristics ... 14 SPI Accessible Features .. 35 Equivalent Circuits ... 18 Memory Map .. 36 Theory of Operation .. 20 Reading the Memory Map Register Table ... 36 ADC Architecture .. 20 Memory Map Register Table ... 37 Analog Input Considerations .. 20 Memory Map Register Description ... 41 Voltage Reference ... 21 Applications Information .. 42 Clock Input Considerations .. 21 Design Guidelines .. 42 Power Dissipation and Standby Mode ... 24 SPI Initialization Sequence ... 42 Digital Outputs ... 25 Outline Dimensions ... 45 JESD204B Transmit Top Level Description .. 25 Ordering Guide .. 45 Rev. E | Page 2 of 45 Document Outline Features Applications Functional Block Diagram Product Highlights Revision History General Description Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Clock Input Considerations Nyquist Clock Input Options RF Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Standby Mode Digital Outputs JESD204B Transmit Top Level Description JESD204B Overview JESD204B Synchronization Details CGS Phase ILAS Phase Data Transmission Phase Link Setup Parameters Disable Lanes Before Changing Configuration Select Quick Configuration Option Configure Detailed Options Check FCHK, Checksum of JESD204B Interface Parameters Additional Digital Output Configuration Options Re-Enable Lanes After Configuration Internal FIFO Timing Optimization Frame and Lane Alignment Monitoring and Correction Digital Outputs and Timing ADC Overrange and Gain Control ADC Overrange (OR) Gain Switching Fast Threshold Detection (FDA and FDB) DC Correction DC Correction Bandwidth DC Correction Readback DC Correction Freeze DC Correction (DCC) Enable Bits Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface SPI Accessible Features Memory Map Reading the Memory Map Register Table Open and Reserved Locations Default Values Logic Levels Channel-Specific Registers Memory Map Register Table Memory Map Register Description Applications Information Design Guidelines Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations VCM SPI Port SPI Initialization Sequence Outline Dimensions Ordering Guide