Datasheet AD9250 (Analog Devices) - 9

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Data Sheet AD9250 SWITCHING SPECIFICATIONS Table 4. AD9250-170 AD9250-250 Parameter Symbol Temperature Min Typ Max Min Typ Max Unit
CLOCK INPUT PARAMETERS Conversion Rate1 fS Full 40 170 40 250 MSPS SYSREF± Setup Time to Rising Edge CLK±2 tREFS Full 0.31 0.31 ns SYSREF± Hold Time from Rising Edge CLK±2 tREFH Full 0 0 ns SYSREF± Setup Time to Rising Edge RFCLK2 tREFSRF Full 0.50 0.50 ns SYSREF± Hold Time from Rising Edge RFCLK2 tREFHRF Full 0 0 ns CLK± Pulse Width High tCH Divide-by-1 Mode, DCS Enabled Full 2.61 2.9 3.19 1.8 2.0 2.2 ns Divide-by-1 Mode, DCS Disabled Full 2.76 2.9 3.05 1.9 2.0 2.1 ns Divide-by-2 Mode Through Divide-by-8 Mode Full 0.8 0.8 ns Aperture Delay tA Full 1.0 1.0 ns Aperture Uncertainty (Jitter) tJ Full 0.16 0.16 ps rms DATA OUTPUT PARAMETERS Data Output Period or Unit Interval (UI) Full L/(20 × M × fS) L/(20 × M × fS) Seconds Data Output Duty Cycle 25°C 50 50 % Data Valid Time 25°C 0.84 0.78 UI PLL Lock Time (tLOCK) 25°C 25 25 µs Wake-Up Time Standby 25°C 10 10 µs ADC (Power-Down)3 25°C 250 250 µs Output (Power-Down)4 25°C 50 50 µs Subclass 0: SYNCINB± Falling Edge to First Valid Full 5 5 Multiframes K.28 Characters (Delay Required for Rx CGS Start) Subclass 1: SYSREF± Rising Edge to First Valid K.28 Full 6 6 Multiframes Characters (Delay Required for SYNCB± Rising Edge/Rx CGS Start) CGS Phase K.28 Characters Duration Full 1 1 Multiframes Pipeline Delay JESD204B M1, L1 Mode (Latency) Full 36 36 Cycles5 JESD204B M1, L2 Mode (Latency) Full 59 59 Cycles JESD204B M2, L1 Mode (Latency) Full 25 25 Cycles JESD204B M2, L2 Mode (Latency) Full 36 36 Cycles Fast Detect (Latency) Full 7 7 Cycles Data Rate per Lane Full 3.4 5.0 5.0 Gbps Uncorrelated Bounded High Probability (UBHP) Jitter 25°C 6 8 ps Random Jitter At 3.4 Gbps Full 2.3 ps rms At 5.0 Gbps Full 1.7 ps rms Output Rise/Fall Time Full 60 60 ps Differential Termination Resistance 25°C 100 100 Ω Out-of-Range Recovery Time Full 3 3 Cycles 1 Conversion rate is the clock rate after the divider. 2 Refer to Figure 3 for timing diagram. 3 Wake-up time ADC is defined as the time required for the ADC to return to normal operation from power-down mode. 4 Wake-up time output is defined as the time required for JESD204B output to return to normal operation from power-down mode. 5 Cycles refers to ADC conversion rate cycles. Rev. E | Page 9 of 45 Document Outline Features Applications Functional Block Diagram Product Highlights Revision History General Description Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Clock Input Considerations Nyquist Clock Input Options RF Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Standby Mode Digital Outputs JESD204B Transmit Top Level Description JESD204B Overview JESD204B Synchronization Details CGS Phase ILAS Phase Data Transmission Phase Link Setup Parameters Disable Lanes Before Changing Configuration Select Quick Configuration Option Configure Detailed Options Check FCHK, Checksum of JESD204B Interface Parameters Additional Digital Output Configuration Options Re-Enable Lanes After Configuration Internal FIFO Timing Optimization Frame and Lane Alignment Monitoring and Correction Digital Outputs and Timing ADC Overrange and Gain Control ADC Overrange (OR) Gain Switching Fast Threshold Detection (FDA and FDB) DC Correction DC Correction Bandwidth DC Correction Readback DC Correction Freeze DC Correction (DCC) Enable Bits Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface SPI Accessible Features Memory Map Reading the Memory Map Register Table Open and Reserved Locations Default Values Logic Levels Channel-Specific Registers Memory Map Register Table Memory Map Register Description Applications Information Design Guidelines Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations VCM SPI Port SPI Initialization Sequence Outline Dimensions Ordering Guide