Datasheet AD7176-2 (Analog Devices)
| 制造商 | Analog Devices |
| 描述 | 24-Bit, 250 kSPS Sigma Delta ADC with 20 µs Settling |
| 页数 / 页 | 69 / 1 — 24-Bit, 250 kSPS Sigma-Delta ADC. with 20 µs Settling. Data Sheet. … |
| 修订版 | D |
| 文件格式/大小 | PDF / 1.1 Mb |
| 文件语言 | 英语 |
24-Bit, 250 kSPS Sigma-Delta ADC. with 20 µs Settling. Data Sheet. AD7176-2. FEATURES. GENERAL DESCRIPTION
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24-Bit, 250 kSPS Sigma-Delta ADC with 20 µs Settling Data Sheet AD7176-2 FEATURES GENERAL DESCRIPTION Fast and flexible output rate—5 SPS to 250 kSPS
The AD7176-2 is a fast settling, highly accurate, high resolution,
Fast settling time—20 µs
multiplexed Σ-Δ analog-to-digital converter (ADC) for low band-
Channel scan data rate of 50 kSPS/channel
width input signals. Its inputs can be configured as two fully
Performance specifications
differential or four pseudo differential inputs via the integrated
17 noise free bits at 250 kSPS
crosspoint multiplexer. An integrated precision, 2.5 V, low drift
20 noise free bits at 2.5 kSPS
(2 ppm/°C), band gap internal reference (with an output
22 noise free bits at 5 SPS
reference buffer) adds functionality and reduces the external
INL ±2.5 ppm of FSR
component count.
85 dB rejection of 50 Hz and 60 Hz with 50 ms settling
The maximum channel scan data rate is 50 kSPS/channel
User-configurable input channels
(settling time of 20 µs), resulting in ful y settled data with
2 fully differential or 4 pseudo differential
17 noise free bits. User-selectable output data rates range from
Crosspoint multiplexer
5 SPS to 250 kSPS. The resolution increases at lower speeds.
On-chip 2.5 V reference (drift 2 ppm/°C) Internal oscillator, external crystal, or external clock
The AD7176-2 offers three key digital filters. The fast settling
Power supply
sinc5 + sinc1 filter maximizes the channel scan rate. The sinc3
Single supply: 5 V AVDD1, 2 V to 5 V AVDD2 and IOVDD
filter maximizes the resolution for single-channel, low speed
Optional split supply: AVDD1 and AVSS ± 2.5 V
applications. For 50 Hz and 60 Hz environments, the AD7176-2
Current: 7.8 mA
specific filter minimizes the settling times or maximizes the
Temperature range: −40°C to +105°C
rejection of the line frequency. These enhanced filters enable
3- or 4-wire serial digital interface (Schmitt trigger on SCLK)
simultaneous 50 Hz and 60 Hz rejection with a 27 SPS output
CRC error checking
data rate (with a settling time of 36 ms).
SPI, QSPI, MICROWIRE, and DSP compatible
System offset and gain errors can be corrected on a per channel
APPLICATIONS
basis. This per channel configurability extends to the output data rate used for each channel when using a sinc5 + sinc1 filter. All
Process control: PLC/DCS modules
switching of the crosspoint multiplexer is controlled by the ADC
Temperature and pressure measurement
and can be configured to automatical y control an external
Medical and scientific multichannel instrumentation
multiplexer via the GPIO pins.
Chromatography
The specified operating temperature range is −40°C to +105°C. The AD7176-2 is housed in a 24-lead TSSOP package.
FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD2 REGCAPA REF– REF+ REFOUT IOVDD REGCAPD BUFFERED 1.8V 1.8V PRECISION LDO LDO REFERENCE INT REF AIN0 CS AIN1 SCLK SERIAL Σ-Δ ADC DIGITAL INTERFACE DIN AIN2 FILTER AND CONTROL DOUT/RDY AIN3 SYNC/ERROR GPIO AND XTAL AND INTERNAL MUX CLOCK OSCILLATOR AIN4 I/O CONTROL CIRCUITRY CROSSPOINT AD7176-2 MULTIPLEXER
001
AVSS GPIO0 GPIO1 XTAL1 CLKIO/XTAL2 DGND
1037- 1 Figure 1.
Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2012–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES DIGITAL COMMUNICATION Accessing the ADC Register Map AD7176-2 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Offset Registers Gain Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION ANALOG INPUT Fully Differential Inputs Pseudo Differential Inputs DRIVER AMPLIFIERS AD8475 AD8656 ADA4940-1/ADA4940-2 AD7176-2 REFERENCE External Reference Internal Reference AD7176-2 CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER SINGLE CYCLE SETTLING ENHANCED 50 HZ AND 60 HZ REJECTION FILTERS OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION MODES DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE I/O EXTERNAL MULTIPLEXER CONTROL DELAY 16-BIT/24-BIT CONVERSIONS SERIAL INTERFACE RESET (DOUT_RESET) SYNCHRONIZATION (SYNC\/ERROR\) ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR Pin DATA_STAT IOSTRENTGH GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL MAP REGISTER 0 CHANNEL MAP REGISTER 1 CHANNEL MAP REGISTER 2 CHANNEL MAP REGISTER 3 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 SETUP CONFIGURATION REGISTER 2 SETUP CONFIGURATION REGISTER 3 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 FILTER CONFIGURATION REGISTER 2 FILTER CONFIGURATION REGISTER 3 OFFSET REGISTER 0 OFFSET REGISTER 1 OFFSET REGISTER 2 OFFSET REGISTER 3 GAIN REGISTER 0 GAIN REGISTER 1 GAIN REGISTER 2 GAIN REGISTER 3 OUTLINE DIMENSIONS ORDERING GUIDE
The AD7176-2 is a fast settling, highly accurate, high resolution,
Fast settling time—20 µs
multiplexed Σ-Δ analog-to-digital converter (ADC) for low band-
Channel scan data rate of 50 kSPS/channel
width input signals. Its inputs can be configured as two fully
Performance specifications
differential or four pseudo differential inputs via the integrated
17 noise free bits at 250 kSPS
crosspoint multiplexer. An integrated precision, 2.5 V, low drift
20 noise free bits at 2.5 kSPS
(2 ppm/°C), band gap internal reference (with an output
22 noise free bits at 5 SPS
reference buffer) adds functionality and reduces the external
INL ±2.5 ppm of FSR
component count.
85 dB rejection of 50 Hz and 60 Hz with 50 ms settling
The maximum channel scan data rate is 50 kSPS/channel
User-configurable input channels
(settling time of 20 µs), resulting in ful y settled data with
2 fully differential or 4 pseudo differential
17 noise free bits. User-selectable output data rates range from
Crosspoint multiplexer
5 SPS to 250 kSPS. The resolution increases at lower speeds.
On-chip 2.5 V reference (drift 2 ppm/°C) Internal oscillator, external crystal, or external clock
The AD7176-2 offers three key digital filters. The fast settling
Power supply
sinc5 + sinc1 filter maximizes the channel scan rate. The sinc3
Single supply: 5 V AVDD1, 2 V to 5 V AVDD2 and IOVDD
filter maximizes the resolution for single-channel, low speed
Optional split supply: AVDD1 and AVSS ± 2.5 V
applications. For 50 Hz and 60 Hz environments, the AD7176-2
Current: 7.8 mA
specific filter minimizes the settling times or maximizes the
Temperature range: −40°C to +105°C
rejection of the line frequency. These enhanced filters enable
3- or 4-wire serial digital interface (Schmitt trigger on SCLK)
simultaneous 50 Hz and 60 Hz rejection with a 27 SPS output
CRC error checking
data rate (with a settling time of 36 ms).
SPI, QSPI, MICROWIRE, and DSP compatible
System offset and gain errors can be corrected on a per channel
APPLICATIONS
basis. This per channel configurability extends to the output data rate used for each channel when using a sinc5 + sinc1 filter. All
Process control: PLC/DCS modules
switching of the crosspoint multiplexer is controlled by the ADC
Temperature and pressure measurement
and can be configured to automatical y control an external
Medical and scientific multichannel instrumentation
multiplexer via the GPIO pins.
Chromatography
The specified operating temperature range is −40°C to +105°C. The AD7176-2 is housed in a 24-lead TSSOP package.
FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD2 REGCAPA REF– REF+ REFOUT IOVDD REGCAPD BUFFERED 1.8V 1.8V PRECISION LDO LDO REFERENCE INT REF AIN0 CS AIN1 SCLK SERIAL Σ-Δ ADC DIGITAL INTERFACE DIN AIN2 FILTER AND CONTROL DOUT/RDY AIN3 SYNC/ERROR GPIO AND XTAL AND INTERNAL MUX CLOCK OSCILLATOR AIN4 I/O CONTROL CIRCUITRY CROSSPOINT AD7176-2 MULTIPLEXER
001
AVSS GPIO0 GPIO1 XTAL1 CLKIO/XTAL2 DGND
1037- 1 Figure 1.
Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2012–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES DIGITAL COMMUNICATION Accessing the ADC Register Map AD7176-2 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Offset Registers Gain Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION ANALOG INPUT Fully Differential Inputs Pseudo Differential Inputs DRIVER AMPLIFIERS AD8475 AD8656 ADA4940-1/ADA4940-2 AD7176-2 REFERENCE External Reference Internal Reference AD7176-2 CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER SINGLE CYCLE SETTLING ENHANCED 50 HZ AND 60 HZ REJECTION FILTERS OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION MODES DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE I/O EXTERNAL MULTIPLEXER CONTROL DELAY 16-BIT/24-BIT CONVERSIONS SERIAL INTERFACE RESET (DOUT_RESET) SYNCHRONIZATION (SYNC\/ERROR\) ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR Pin DATA_STAT IOSTRENTGH GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL MAP REGISTER 0 CHANNEL MAP REGISTER 1 CHANNEL MAP REGISTER 2 CHANNEL MAP REGISTER 3 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 SETUP CONFIGURATION REGISTER 2 SETUP CONFIGURATION REGISTER 3 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 FILTER CONFIGURATION REGISTER 2 FILTER CONFIGURATION REGISTER 3 OFFSET REGISTER 0 OFFSET REGISTER 1 OFFSET REGISTER 2 OFFSET REGISTER 3 GAIN REGISTER 0 GAIN REGISTER 1 GAIN REGISTER 2 GAIN REGISTER 3 OUTLINE DIMENSIONS ORDERING GUIDE