Datasheet AD7176-2 (Analog Devices) - 4
| 制造商 | Analog Devices |
| 描述 | 24-Bit, 250 kSPS Sigma Delta ADC with 20 µs Settling |
| 页数 / 页 | 69 / 4 — Data Sheet. AD7176-2. REVISION HISTORY 3/16—Rev. C to Rev. D. 6/15—Rev. B … |
| 修订版 | D |
| 文件格式/大小 | PDF / 1.1 Mb |
| 文件语言 | 英语 |
Data Sheet. AD7176-2. REVISION HISTORY 3/16—Rev. C to Rev. D. 6/15—Rev. B to Rev. C. 10/14—Rev. A to Rev. B. 4/13—Rev.0 to Rev. A
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Data Sheet AD7176-2 REVISION HISTORY 3/16—Rev. C to Rev. D
Reordered Figure 56 to Figure 63 ... 35 Changes to Power Supplies Section .. 19 Changes to Figure 65 .. 38 Added AD7176-2 Reset Section .. 20 Changes to Standby and Power-Down Modes Section .. 40 Changes to Digital Interface Section and Figure 68 ... 41
6/15—Rev. B to Rev. C
Changes to CRC Calculation Example ... 42 Changes to Figure 8 .. 11 Added Integrated Function Section and Delay Section; Changes to General-Purpose I/O Section and Normal Synchronization
10/14—Rev. A to Rev. B
Section .. 44 Changes to General Description ... 1 Changed Register 0x02 Bits[2:1] to HIDE_DELAY ... 47 Changes to Figure 1 .. 1 Changes to Table 23 .. 49 Changes to Table 1 .. 4 Changes to Table 26 .. 52 Added ESD Rating (HBM) of 3.5 kV; Table 3 and Changes Changes to Table 29 .. 54 to Table 4 .. 8 Changes to Table 31 .. 56 Changes to Figure 5 to Figure 10 Captions .. 11 Changes to Table 32 .. 57 Changes to Figure 11 to Figure 16 Captions ... 12 Changes to Table 33 .. 58 Changes to Figure 17 to Figure 22 Captions ... 13 Changes to Table 34 .. 59 Changes to Figure 23 Caption; Added Figure 24 to Figure 28; Changes to Table 39 .. 62 Renumbered Sequential y .. 14 Changes to Table 40 .. 63 Added Figure 29 to Figure 34 .. 15 Changes to Table 41 .. 64 Added Figure 35 to Figure 36 .. 16 Changes to Table 42 .. 65 Changes to Noise Performance and Resolution Section .. 17 Changes to Getting Started Section and Figure 37 ... 18
4/13—Rev.0 to Rev. A
Changes to Configuration Overview Section .. 21 Changes to Table 20 .. 31 Changes to Digital Filters Section and Table 19 .. 31 Changes to Sinc3 Filter Section ... 32
11/12—Revision 0—Initial Version
Changes to Table 20 .. 33 Rev. D | Page 3 of 68 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES DIGITAL COMMUNICATION Accessing the ADC Register Map AD7176-2 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Offset Registers Gain Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION ANALOG INPUT Fully Differential Inputs Pseudo Differential Inputs DRIVER AMPLIFIERS AD8475 AD8656 ADA4940-1/ADA4940-2 AD7176-2 REFERENCE External Reference Internal Reference AD7176-2 CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER SINGLE CYCLE SETTLING ENHANCED 50 HZ AND 60 HZ REJECTION FILTERS OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION MODES DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE I/O EXTERNAL MULTIPLEXER CONTROL DELAY 16-BIT/24-BIT CONVERSIONS SERIAL INTERFACE RESET (DOUT_RESET) SYNCHRONIZATION (SYNC\/ERROR\) ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR Pin DATA_STAT IOSTRENTGH GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL MAP REGISTER 0 CHANNEL MAP REGISTER 1 CHANNEL MAP REGISTER 2 CHANNEL MAP REGISTER 3 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 SETUP CONFIGURATION REGISTER 2 SETUP CONFIGURATION REGISTER 3 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 FILTER CONFIGURATION REGISTER 2 FILTER CONFIGURATION REGISTER 3 OFFSET REGISTER 0 OFFSET REGISTER 1 OFFSET REGISTER 2 OFFSET REGISTER 3 GAIN REGISTER 0 GAIN REGISTER 1 GAIN REGISTER 2 GAIN REGISTER 3 OUTLINE DIMENSIONS ORDERING GUIDE
Reordered Figure 56 to Figure 63 ... 35 Changes to Power Supplies Section .. 19 Changes to Figure 65 .. 38 Added AD7176-2 Reset Section .. 20 Changes to Standby and Power-Down Modes Section .. 40 Changes to Digital Interface Section and Figure 68 ... 41
6/15—Rev. B to Rev. C
Changes to CRC Calculation Example ... 42 Changes to Figure 8 .. 11 Added Integrated Function Section and Delay Section; Changes to General-Purpose I/O Section and Normal Synchronization
10/14—Rev. A to Rev. B
Section .. 44 Changes to General Description ... 1 Changed Register 0x02 Bits[2:1] to HIDE_DELAY ... 47 Changes to Figure 1 .. 1 Changes to Table 23 .. 49 Changes to Table 1 .. 4 Changes to Table 26 .. 52 Added ESD Rating (HBM) of 3.5 kV; Table 3 and Changes Changes to Table 29 .. 54 to Table 4 .. 8 Changes to Table 31 .. 56 Changes to Figure 5 to Figure 10 Captions .. 11 Changes to Table 32 .. 57 Changes to Figure 11 to Figure 16 Captions ... 12 Changes to Table 33 .. 58 Changes to Figure 17 to Figure 22 Captions ... 13 Changes to Table 34 .. 59 Changes to Figure 23 Caption; Added Figure 24 to Figure 28; Changes to Table 39 .. 62 Renumbered Sequential y .. 14 Changes to Table 40 .. 63 Added Figure 29 to Figure 34 .. 15 Changes to Table 41 .. 64 Added Figure 35 to Figure 36 .. 16 Changes to Table 42 .. 65 Changes to Noise Performance and Resolution Section .. 17 Changes to Getting Started Section and Figure 37 ... 18
4/13—Rev.0 to Rev. A
Changes to Configuration Overview Section .. 21 Changes to Table 20 .. 31 Changes to Digital Filters Section and Table 19 .. 31 Changes to Sinc3 Filter Section ... 32
11/12—Revision 0—Initial Version
Changes to Table 20 .. 33 Rev. D | Page 3 of 68 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES DIGITAL COMMUNICATION Accessing the ADC Register Map AD7176-2 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Offset Registers Gain Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION ANALOG INPUT Fully Differential Inputs Pseudo Differential Inputs DRIVER AMPLIFIERS AD8475 AD8656 ADA4940-1/ADA4940-2 AD7176-2 REFERENCE External Reference Internal Reference AD7176-2 CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER SINGLE CYCLE SETTLING ENHANCED 50 HZ AND 60 HZ REJECTION FILTERS OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION MODES DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE I/O EXTERNAL MULTIPLEXER CONTROL DELAY 16-BIT/24-BIT CONVERSIONS SERIAL INTERFACE RESET (DOUT_RESET) SYNCHRONIZATION (SYNC\/ERROR\) ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR Pin DATA_STAT IOSTRENTGH GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL MAP REGISTER 0 CHANNEL MAP REGISTER 1 CHANNEL MAP REGISTER 2 CHANNEL MAP REGISTER 3 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 SETUP CONFIGURATION REGISTER 2 SETUP CONFIGURATION REGISTER 3 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 FILTER CONFIGURATION REGISTER 2 FILTER CONFIGURATION REGISTER 3 OFFSET REGISTER 0 OFFSET REGISTER 1 OFFSET REGISTER 2 OFFSET REGISTER 3 GAIN REGISTER 0 GAIN REGISTER 1 GAIN REGISTER 2 GAIN REGISTER 3 OUTLINE DIMENSIONS ORDERING GUIDE