Datasheet AD9633 (Analog Devices) - 5

AD9633 Data Sheet AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 2. AD9633-80 AD9633-105 AD9633-125 Parameter1 Temp Min Typ Max Min Typ Max Min Typ Max Unit
SIGNAL-TO-NOISE RATIO (SNR) fIN = 9.7 MHz 25°C 71.7 71.7 71.8 dBFS fIN = 30.5 MHz 25°C 71.7 71.6 71.4 dBFS fIN = 70 MHz Full 70.0 70.5 70.2 71.0 70.5 71.1 dBFS fIN = 140 MHz 25°C 70.3 70.2 70.0 dBFS fIN = 200 MHz 25°C 69.4 69.8 69.4 dBFS SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD) fIN = 9.7 MHz 25°C 71.6 71.6 71.1 dBFS fIN = 30.5 MHz 25°C 71.5 71.5 71.3 dBFS fIN = 70 MHz Full 70.0 70.4 69.5 70.9 70.5 71.0 dBFS fIN = 140 MHz 25°C 70.2 69.9 69.9 dBFS fIN = 200 MHz 25°C 68.4 68.7 67.4 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 9.7 MHz 25°C 11.6 11.6 11.5 Bits fIN = 30.5 MHz 25°C 11.6 11.6 11.5 Bits fIN = 70 MHz Full 11.3 11.5 11.3 11.6 11.4 11.5 Bits fIN = 140 MHz 25°C 11.4 11.3 11.3 Bits fIN = 200 MHz 25°C 11.2 11.2 10.9 Bits SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 9.7 MHz 25°C 96 94 94 dBc fIN = 30.5 MHz 25°C 90 89 91 dBc fIN = 70 MHz Full 76 96 75 87 75 91 dBc fIN = 140 MHz 25°C 87 91 86 dBc fIN = 200 MHz 25°C 86 88 86 dBc WORST HARMONIC (SECOND OR THIRD) fIN = 9.7 MHz 25°C −96 −94 −94 dBc fIN = 30.5 MHz 25°C −90 −89 −91 dBc fIN = 70 MHz Full −96 −76 −87 −75 −91 −75 dBc fIN = 140 MHz 25°C −87 −91 −86 dBc fIN = 200 MHz 25°C −86 −88 −86 dBc WORST OTHER (EXCLUDING SECOND OR THIRD) fIN = 9.7 MHz 25°C −97 −96 −94 dBc fIN = 30.5 MHz 25°C −95 −93 −97 dBc fIN = 70 MHz Full −96 −82 −94 −82 −96 −84 dBc fIN = 140 MHz 25°C −97 −93 −92 dBc fIN = 200 MHz 25°C −96 −93 −90 dBc TWO-TONE INTERMODULATION DISTORTION (IMD)—AIN1 AND AIN2 = −7.0 dBFS fIN1 = 70.5 MHz, fIN2 = 72.5 MHz 25°C 85 86 87 dBc CROSSTALK2 Full −95 −95 −95 dB CROSSTALK (OVERRANGE CONDITION)3 25°C −89 −89 −89 dB POWER SUPPLY REJECTION RATIO (PSRR)1, 4 AVDD 25°C 52 52 52 dB DRVDD 25°C 75 75 75 dB ANALOG INPUT BANDWIDTH, FULL POWER 25°C 650 650 650 MHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 2 Crosstalk is measured at 70 MHz with −1.0 dBFS analog input on one channel and no input on the adjacent channel. 3 Overrange condition is specified as being 3 dB above the ful -scale input range. 4 PSRR is measured by injecting a sinusoidal signal at 10 MHz to the power supply pin and measuring the output spur on the FFT. PSRR is calculated as the ratio of the amplitudes of the spur voltage over the pin voltage, expressed in decibels. Rev. B | Page 4 of 41 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Table of Contents Revision History Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics AD9633-80 AD9633-105 AD9633-125 Equivalent Circuits Theory of Operation Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO/OLM Pin SCLK/DTP Pin CSB Pin RBIAS Pin Output Test Modes Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Channel-Specific Registers Memory Map Register Table Memory Map Register Descriptions Device Index (Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bits[7:6]—Open Bit 5—External Power-Down Pin Function Bits[4:2]—Open Bits[1:0]—Power Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—Open Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—Open Bit 2—Output Invert Bit 1—Open Bit 0—Output Format Output Adjust (Register 0x15) Bits[7:6]—Open Bits[5:4]—Output Driver Termination Bits[3:1]—Open Bit 0—Output Drive Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Serial Output Data Control (Register 0x21) Resolution/Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open Applications Information Design Guidelines Power and Ground Recommendations Clock Stability Considerations Exposed Pad Thermal Heat Slug Recommendations VCM Reference Decoupling SPI Port Crosstalk Performance Outline Dimensions Ordering Guide