Datasheet AD9484 (Analog Devices) - 4
| 制造商 | Analog Devices |
| 描述 | 8-Bit, 500 MSPS, 1.8 V Analog-to-Digital Converter |
| 页数 / 页 | 25 / 4 — AD9484. SPECIFICATIONS DC SPECIFICATIONS. Table. . Parameter. Temp. Min. … |
| 修订版 | A |
| 文件格式/大小 | PDF / 637 Kb |
| 文件语言 | 英语 |
AD9484. SPECIFICATIONS DC SPECIFICATIONS. Table. . Parameter. Temp. Min. Typ. Max. Unit
该数据表的模型线
文件文字版本
link to page 25 link to page 25 link to page 25 link to page 25 link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 link to page 21
AD9484 SPECIFICATIONS DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted.
Table
1
. Parameter 1 Temp Min Typ Max Unit
RESOLUTION 8 Bits ACCURACY No Missing Codes Full Guaranteed Offset Error 25°C 0 mV Full −3.0 +3.0 mV Gain Error 25°C 1.0 % FS Full −5.0 +7.0 % FS Differential Nonlinearity (DNL) 25°C ±0.13 LSB Full −0.25 +0.25 LSB Integral Nonlinearity (INL) 25°C ±0.1 LSB Full −0.15 +0.15 LSB INTERNAL REFERENCE VREF Full 0.71 0.75 0.78 V TEMPERATURE DRIFT Offset Error Full 18 μV/°C Gain Error Full 0.07 %/°C ANALOG INPUTS (VIN+, VIN−) Differential Input Voltage Range2 Full 1.18 1.5 1.6 V p-p Input Common-Mode Voltage Full 1.7 V Input Resistance (Differential) Full 1 kΩ Input Capacitance (Differential) Full 1.3 pF POWER SUPPLY AVDD Full 1.75 1.8 1.9 V DRVDD Full 1.75 1.8 1.9 V Supply Currents I 3 AVDD Full 283 300 mA I 3 DRVDD /SDR Mode4 Full 89 100 mA Power Dissipation SDR Mode4 Full 670 720 mW Standby Mode Full 40 50 mW Power-Down Mode Full 2.5 7 mW 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 The input range is programmable through the SPI, and the range specified reflects the nominal values of each setting. See the Memory Ma sect p ion. 3 IAVDD and IDRVDD are measured with a −1 dBFS, 10.3 MHz sine input at a rated sample rate. 4 Single data rate mode; this is the default mode of the AD9484. Rev. A | Page 3 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE Differential Input Configurations CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS Digital Outputs and Timing Output Data Rate and Pinout Configuration Out-of-Range (OR) TIMING VREF AD9484 CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS OUTLINE DIMENSIONS ORDERING GUIDE
AD9484 SPECIFICATIONS DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted.
Table
1
. Parameter 1 Temp Min Typ Max Unit
RESOLUTION 8 Bits ACCURACY No Missing Codes Full Guaranteed Offset Error 25°C 0 mV Full −3.0 +3.0 mV Gain Error 25°C 1.0 % FS Full −5.0 +7.0 % FS Differential Nonlinearity (DNL) 25°C ±0.13 LSB Full −0.25 +0.25 LSB Integral Nonlinearity (INL) 25°C ±0.1 LSB Full −0.15 +0.15 LSB INTERNAL REFERENCE VREF Full 0.71 0.75 0.78 V TEMPERATURE DRIFT Offset Error Full 18 μV/°C Gain Error Full 0.07 %/°C ANALOG INPUTS (VIN+, VIN−) Differential Input Voltage Range2 Full 1.18 1.5 1.6 V p-p Input Common-Mode Voltage Full 1.7 V Input Resistance (Differential) Full 1 kΩ Input Capacitance (Differential) Full 1.3 pF POWER SUPPLY AVDD Full 1.75 1.8 1.9 V DRVDD Full 1.75 1.8 1.9 V Supply Currents I 3 AVDD Full 283 300 mA I 3 DRVDD /SDR Mode4 Full 89 100 mA Power Dissipation SDR Mode4 Full 670 720 mW Standby Mode Full 40 50 mW Power-Down Mode Full 2.5 7 mW 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 The input range is programmable through the SPI, and the range specified reflects the nominal values of each setting. See the Memory Ma sect p ion. 3 IAVDD and IDRVDD are measured with a −1 dBFS, 10.3 MHz sine input at a rated sample rate. 4 Single data rate mode; this is the default mode of the AD9484. Rev. A | Page 3 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE Differential Input Configurations CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS Digital Outputs and Timing Output Data Rate and Pinout Configuration Out-of-Range (OR) TIMING VREF AD9484 CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS OUTLINE DIMENSIONS ORDERING GUIDE