Datasheet AD9484 (Analog Devices) - 9

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AD9484 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS D D + – N D D – + D C C C C C C O O G V D K K D N N N N N N C C R R V L L V D D D D D D D D D D A C C A 6 5 4 3 2 1 0 9 8 7 6 5 5 5 5 5 5 4 3 5 5 4 4 4 4 4 4 4 DNC 1 PIN 1 42 AVDD INDICATOR DNC 2 41 AVDD D0– 3 40 CML D0+ 4 39 AVDD D1– 5 38 AVDD D1+ 6 37 AVDD AD9484 DRVDD 7 36 VIN– DRGND 8 TOP VIEW 35 VIN+ D2– 9 (Not to Scale) 34 AVDD D2+ 10 33 AVDD D3– 11 32 AVDD D3+ 12 31 VREF D4– 13 PIN 0 (EXPOSED PADDLE) = AGND 30 AVDD D4+ 14 29 PWDN 5 6 7 8 0 1 1 1 1 9 1 1 2 2 22 32 42 52 62 72 82 – + + – 5 + – – + 5 6 6 7 7 S R D D OI B C D R F D D D D D N D S N O O G V D D/ C D R R S K D D L C S NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. AGND AND DRGND SHOULD BE TIED TO A COMMON QUIET GROUND PLANE.
3
3. THE EXPOSED PADDLE MUST BE SOLDERED TO
-00
A GROUND PLANE.
615 09 Figure 3. Pin Configuration
Table 7. Pin Function Descriptions Pin No. Mnemonic Description
0 AGND1 Analog Ground. The exposed paddle must be soldered to a ground plane. 30, 32 to 34, 37 to 39, AVDD 1.8 V Analog Supply. 41 to 43, 46 7, 24, 47 DRVDD 1.8 V Digital Output Supply. 8, 23, 48 DRGND1 Digital Output Ground. 35 VIN+ Analog Input—True. 36 VIN− Analog Input—Complement. 40 CML Common-Mode Output. Enabled through the SPI, this pin provides a reference for the optimized internal bias voltage for VIN+/VIN−. 44 CLK+ Clock Input—True. 45 CLK− Clock Input—Complement. 31 VREF Voltage Reference Internal/Input/Output. Nominally 0.75 V. 1, 2, 28, 51 to 56 DNC Do Not Connect. Do not connect to this pin. This pin should be left floating. 25 SDIO Serial Port Interface (SPI) Data Input/Output. 26 SCLK/DFS Serial Port Interface Clock (Serial Port Mode)/Data Format Select (External Pin Mode). 27 CSB Serial Port Chip Select (Active Low). 29 PWDN Chip Power-Down. 49 DCO− Data Clock Output—Complement. 50 DCO+ Data Clock Output—True. 3 D0− D0 Complement Output (LSB). 4 D0+ D0 True Output (LSB). 5 D1− D1 Complement Output. 6 D1+ D1 True Output. 9 D2− D2 Complement Output. 10 D2+ D2 True Output. 11 D3− D3 Complement Output. 12 D3+ D3 True Output. 13 D4− D4 Complement Output. Rev. A | Page 8 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE Differential Input Configurations CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS Digital Outputs and Timing Output Data Rate and Pinout Configuration Out-of-Range (OR) TIMING VREF AD9484 CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS OUTLINE DIMENSIONS ORDERING GUIDE