Datasheet AD9434 (Analog Devices) - 7
| 制造商 | Analog Devices |
| 描述 | 12-Bit, 370 MSPS/500 MSPS, 1.8 V Analog-to-Digital Converter |
| 页数 / 页 | 29 / 7 — AD9434. Data Sheet. SWITCHING SPECIFICATIONS. Table 4. AD9434-370. … |
| 修订版 | B |
| 文件格式/大小 | PDF / 937 Kb |
| 文件语言 | 英语 |
AD9434. Data Sheet. SWITCHING SPECIFICATIONS. Table 4. AD9434-370. AD9434-500. Parameter. Temp. Min. Typ. Max. Unit
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AD9434 Data Sheet SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted.
Table 4. AD9434-370 AD9434-500 Parameter Temp Min Typ Max Min Typ Max Unit
Maximum Conversion Rate Full 370 500 MSPS Minimum Conversion Rate Full 50 50 MSPS CLK+ Pulse Width High (tCH)1, 2 Full 1.1 11 0.9 11 ns CLK+ Pulse Width Low (tCL) Full 1.1 11 0.9 11 ns Output (LVDS—SDR Mode)1 Data Propagation Delay (tPD) Full 3.55 3.55 ns Rise Time (tR) (20% to 80%) 25°C 0.15 0.15 ns Fall Time (tF) (20% to 80%) 25°C 0.15 0.15 ns DCO Propagation Delay (tCPD) Full 3.3 3.3 ns Data to DCO Skew (tSKEW) Full 0.15 0.38 0.15 0.38 ns Latency Full 15 15 Cycles Output (LVDS—DDR Mode)2 Data Propagation Delay (tPD) Full 3.3 3.3 ns Rise Time (tR) (20% to 80%) 25°C 0.15 0.15 ns Fall Time (tF) (20% to 80%) 25°C 0.15 0.15 ns DCO Propagation Delay (tCPD) Full 3.3 3.3 ns Data to DCO Skew (tSKEW) Full −0.07 +0.07 −0.07 +0.07 ns Latency Full 15 15 Cycles Aperture Time (tA) 25°C 0.85 0.85 ns Aperture Uncertainty (Jitter, tJ) 25°C 80 80 fs rms 1 See Figure 2. 2 See Figure 3. Rev. B | Page 6 of 28 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation Analog Input and Voltage Reference Differential Input Configurations Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs Digital Outputs and Timing Output Data Rate and Pinout Configuration Out-of-Range (OR) Timing VREF AD9434 Configuration Using the SPI Using the AD9434 to Replace the AD9230 Hardware Interface Configuration Without the SPI Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Outline Dimensions Ordering Guide
AD9434 Data Sheet SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted.
Table 4. AD9434-370 AD9434-500 Parameter Temp Min Typ Max Min Typ Max Unit
Maximum Conversion Rate Full 370 500 MSPS Minimum Conversion Rate Full 50 50 MSPS CLK+ Pulse Width High (tCH)1, 2 Full 1.1 11 0.9 11 ns CLK+ Pulse Width Low (tCL) Full 1.1 11 0.9 11 ns Output (LVDS—SDR Mode)1 Data Propagation Delay (tPD) Full 3.55 3.55 ns Rise Time (tR) (20% to 80%) 25°C 0.15 0.15 ns Fall Time (tF) (20% to 80%) 25°C 0.15 0.15 ns DCO Propagation Delay (tCPD) Full 3.3 3.3 ns Data to DCO Skew (tSKEW) Full 0.15 0.38 0.15 0.38 ns Latency Full 15 15 Cycles Output (LVDS—DDR Mode)2 Data Propagation Delay (tPD) Full 3.3 3.3 ns Rise Time (tR) (20% to 80%) 25°C 0.15 0.15 ns Fall Time (tF) (20% to 80%) 25°C 0.15 0.15 ns DCO Propagation Delay (tCPD) Full 3.3 3.3 ns Data to DCO Skew (tSKEW) Full −0.07 +0.07 −0.07 +0.07 ns Latency Full 15 15 Cycles Aperture Time (tA) 25°C 0.85 0.85 ns Aperture Uncertainty (Jitter, tJ) 25°C 80 80 fs rms 1 See Figure 2. 2 See Figure 3. Rev. B | Page 6 of 28 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation Analog Input and Voltage Reference Differential Input Configurations Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs Digital Outputs and Timing Output Data Rate and Pinout Configuration Out-of-Range (OR) Timing VREF AD9434 Configuration Using the SPI Using the AD9434 to Replace the AD9230 Hardware Interface Configuration Without the SPI Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Outline Dimensions Ordering Guide