Datasheet HMCAD1520 (Analog Devices) - 11
| 制造商 | Analog Devices |
| 描述 | High Speed Multi-Mode 8/12/14-Bit 1000/640/105 MSPS A/D Converter |
| 页数 / 页 | 37 / 11 — HMCAD1520. HigH Speed Multi-Mode 8/12/14-Bit. 1000/640/105 MSpS A/d … |
| 文件格式/大小 | PDF / 1.5 Mb |
| 文件语言 | 英语 |
HMCAD1520. HigH Speed Multi-Mode 8/12/14-Bit. 1000/640/105 MSpS A/d Converter. register initialization. Address. Data. Function
该数据表的模型线
文件文字版本
HMCAD1520
v04.1015
HigH Speed Multi-Mode 8/12/14-Bit 1000/640/105 MSpS A/d Converter register initialization
to set the HMCAD1520 in Precision Mode, the fol owing registers must be changed from the default value. suggested values are:
Address Data Function
sets HMCAD1520 in precision mode, 0x31 0x0008 Clock divider to 1 0x53 0x0004 sets the LvDs output in dual 8 bit mode
Serial interface
the HMCAD1520 configuration registers can be accessed through a serial interface formed by the pins sDAtA (serial interface data), sCLK (serial interface clock) and Csn (chip select, active low). the following occurs when Csn is set low: • serial data are shifted into the chip 0 • At every rising edge of sCLK, the value present at sDAtA is latched • sDAtA is loaded into the register every 24th rising edge of sCLK t Multiples of 24-bit words data can be loaded within a single active Csn pulse. If more than 24 bits are loaded into M sDAtA during one active Csn pulse, only the first 24 bits are kept. the excess bits are ignored. every 24-bit word s is divided into two parts: • the first eight bits form the register address s - r • the remaining 16 bits form the register data e Acceptable sCLK frequencies are from 20MHz down to a few hertz. Duty-cycle does not have to be tightly controlled. t r
timing diagram
e v Figure 2 shows the timing of the serial port interface. table 4 explains the timing variables used in figure 2. n o tchi tcs thi tck ts tch CSN t t lo h SCLK SDATA A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A / D C Figure 2: serial Port Interface timing
table 4: Serial port interface timing definitions Parameter Description Minimum value Unit
t setup time between Csn and sCLK 8 ns cs t Hold time between Csn and sCLK 8 ns ch t sCLK high time 20 ns hi t sCLK low time 20 ns lo t sCLK period 50 ns ck t Data setup time 5 ns s t Data hold time 5 ns h Informatio For price, delivery, and to place orders: Analog Devices, Inc., One Technology Way, P.O. Box 9106, Norwood, n furnished by Analog Devices is believed to be accurate and reliable. However, no For price, delivery, and to place orders: Analog Devices, Inc., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other MA 02062-9106One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Phone: 781-329-4700 • Order online at www.analog.com
0 - 10
Phone: 781-329-4700 • Order online at www.analog.com Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 1-800-ANALOG-D Application Support: Phone: 1-800-ANALOG-D
v04.1015
HigH Speed Multi-Mode 8/12/14-Bit 1000/640/105 MSpS A/d Converter register initialization
to set the HMCAD1520 in Precision Mode, the fol owing registers must be changed from the default value. suggested values are:
Address Data Function
sets HMCAD1520 in precision mode, 0x31 0x0008 Clock divider to 1 0x53 0x0004 sets the LvDs output in dual 8 bit mode
Serial interface
the HMCAD1520 configuration registers can be accessed through a serial interface formed by the pins sDAtA (serial interface data), sCLK (serial interface clock) and Csn (chip select, active low). the following occurs when Csn is set low: • serial data are shifted into the chip 0 • At every rising edge of sCLK, the value present at sDAtA is latched • sDAtA is loaded into the register every 24th rising edge of sCLK t Multiples of 24-bit words data can be loaded within a single active Csn pulse. If more than 24 bits are loaded into M sDAtA during one active Csn pulse, only the first 24 bits are kept. the excess bits are ignored. every 24-bit word s is divided into two parts: • the first eight bits form the register address s - r • the remaining 16 bits form the register data e Acceptable sCLK frequencies are from 20MHz down to a few hertz. Duty-cycle does not have to be tightly controlled. t r
timing diagram
e v Figure 2 shows the timing of the serial port interface. table 4 explains the timing variables used in figure 2. n o tchi tcs thi tck ts tch CSN t t lo h SCLK SDATA A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A / D C Figure 2: serial Port Interface timing
table 4: Serial port interface timing definitions Parameter Description Minimum value Unit
t setup time between Csn and sCLK 8 ns cs t Hold time between Csn and sCLK 8 ns ch t sCLK high time 20 ns hi t sCLK low time 20 ns lo t sCLK period 50 ns ck t Data setup time 5 ns s t Data hold time 5 ns h Informatio For price, delivery, and to place orders: Analog Devices, Inc., One Technology Way, P.O. Box 9106, Norwood, n furnished by Analog Devices is believed to be accurate and reliable. However, no For price, delivery, and to place orders: Analog Devices, Inc., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other MA 02062-9106One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Phone: 781-329-4700 • Order online at www.analog.com
0 - 10
Phone: 781-329-4700 • Order online at www.analog.com Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 1-800-ANALOG-D Application Support: Phone: 1-800-ANALOG-D