Datasheet AD9467 (Analog Devices)

16-Bit, 200 MSPS/250 MSPS Analog-to-Digital Converter Data Sheet AD9467 FEATURES FUNCTIONAL BLOCK DIAGRAM 75.5 dBFS SNR to 210 MHz at 250 MSPS AVDD1 AVDD2 AVDD3 SPIVDD DRVDD (1.8V) (3.3V) (1.8V) (1.8V TO 3.3V) (1.8V) 90 dBFS SFDR to 300 MHz at 250 MSPS CSB SFDR at 170 MHz at 250 MSPS AD9467 SDIO 92 dBFS at −1 dBFS BUFFER SCLK 100 dBFS at −2 dBFS VIN+ 16 PIPELINE 2 60 fs rms jitter VIN– ADC LVDS OR+/OR– OUTPUT D15+/D15– Excellent linearity at 250 MSPS 16 STAGING TO DNL = ±0.5 LSB typical D0+/D0– CLK+ CLOCK 2 INL = ±3.5 LSB typical AND TIMING DCO+/DCO– CLK– MANAGEMENT REF 2 V p-p to 2.5 V p-p (default) differential full-scale input (programmable)
001
Integrated input buffer AGND XVREF DRGND
09029-
External reference support option
Figure 1.
Clock duty cycle stabilizer Output clock available Serial port control Built-in selectable digital test pattern generation Selectable output data format LVDS outputs (ANSI-644 compatible) 1.8 V and 3.3 V supply operation APPLICATIONS
A data clock output (DCO) for capturing data on the output is provided for signaling a new output bit.
Multicarrier, multimode cellular receivers
The internal power-down feature supported via the SPI typically
Antenna array positioning
consumes less than 5 mW when disabled.
Power amplifier linearization Broadband wireless
Optional features allow users to implement various selectable
Radar
operating conditions, including input range, data format select,
Infrared imaging
and output data test patterns.
Communications instrumentation
The AD9467 is available in a Pb-free, 72-lead, LFCSP specified over the −40°C to +85°C industrial temperature range.
GENERAL DESCRIPTION PRODUCT HIGHLIGHTS
The AD9467 is a 16-bit, monolithic, IF sampling analog-to- 1. IF optimization capability used to improve SFDR. digital converter (ADC). It is optimized for high performance 2. Outstanding SFDR performance for IF sampling over wide bandwidths and ease of use. The product operates at a applications such as multicarrier, multimode 3G, and 4G 250 MSPS conversion rate and is designed for wireless receivers, cellular base station receivers. instrumentation, and test equipment that require a high 3. Ease of use: on-chip reference, high input impedance dynamic range. buffer, adjustable analog input range, and an output clock The ADC requires 1.8 V and 3.3 V power supplies and a low to simplify data capture. voltage differential input clock for ful performance operation. 4. Packaged in a Pb-free, 72-lead LFCSP package. No external reference or driver components are required for 5. Clock duty cycle stabilizer (DCS) maintains overall ADC many applications. Data outputs are LVDS compatible (ANSI-644 performance over a wide range of input clock pulse widths. compatible) and include the means to reduce the overal current 6. Standard serial port interface (SPI) supports various needed for short trace distances. product features and functions, such as data formatting (offset binary, twos complement, or Gray coding).
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Document Outline Features Applications General Description Functional Block Diagram Product Highlights Table of Contents Revision History Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagrams Absolute Maximum Ratings Thermal Impedance ESD Caution Pin Configuration and Function Descriptions Equivalent Circuits Typical Performance Characteristics Theory of Operation Analog Input Considerations SFDR Optimization—Buffer Current Adjustment Differential Input Configurations Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Power Supplies Full-Scale and Reference Options Digital Outputs and Timing Overrange (OR) Output Pins SPI Pins: SCLK, SDIO, CSB Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations Outline Dimensions Ordering Guide