Datasheet AD9650 (Analog Devices) - 5

AD9650 Data Sheet ADC AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.35 V internal reference, DCS disabled, unless otherwise noted.
Table 2. AD9650BCPZ-25 AD9650BCPZ-65 AD9650BCPZ-80 AD9650BCPZ-105 Parameter1 Temp Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
SIGNAL-TO-NOISE RATIO (SNR) fIN = 9.7 MHz 25°C 83 83 83 82.5 dBFS fIN = 30 MHz 25°C 81.5 82 82 82 dBFS Full 81.8 81.5 81.6 80.5 dBFS fIN = 70 MHz 25°C 79.5 81 81 80 dBFS fIN = 141 MHz2 25°C 79.5 80 80 dBFS SIGNAL-TO-NOISE-AND-DISTORTION (SINAD) fIN = 9.7 MHz 25°C 82.2 82 82 82 dBFS fIN = 30 MHz 25°C 80 81.2 82 80.4 dBFS Full 81.5 81 80.7 80 dBFS fIN = 70 MHz 25°C 78 79.2 78.5 78.8 dBFS fIN = 141 MHz2 25°C 75 75.1 75.5 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 9.7 MHz 25°C 13.5 13.5 13.5 13.3 Bits fIN = 30 MHz 25°C 13.0 13.2 13.2 13.2 Bits fIN = 70 MHz 25°C 12.7 13.0 13.0 13.0 Bits fIN = 141 MHz2 25°C 12.9 13.0 12.3 Bits WORST SECOND OR THIRD HARMONIC fIN =9.7 MHz 25°C −95 −94 −95.5 −91 dBc fIN = 30 MHz 25°C −85 −93 −92 −90 dBc Full −91.5 −88 −87 −87 dBc fIN = 70 MHz 25°C −87 −86 −86 −92 dBc fIN = 141 MHz 25°C −79 −79 −80 dBc SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 9.7 MHz 25°C 95 94 95.5 91 dBc fIN = 30 MHz 25°C 85 93 92 90 dBc Full 91.5 88 87 87 dBc fIN = 70 MHz 25°C 87 86 86 92 dBc fIN = 141 MHz 25°C 79 79 80 dBc WORST OTHER (HARMONIC OR SPUR) fIN = 9.7 MHz 25°C −110 −105 −105 −100 dBc fIN = 30 MHz 25°C −102 −105 −105 −101 dBc Full −97 −97 −97 −94 dBc fIN = 70 MHz 25°C −97 −97 −97 −97 dBc fIN = 141 MHz 25°C −97 −97 −88 dBc TWO-TONE SFDR fIN = 7.2 MHz (−7 dBFS ), 8.4 MHz 25°C 87 (−7 dBFS) fIN = 25 MHz (−7 dBFS ), 30 MHz 25°C 84 90 87 87 dBc (−7 dBFS) fIN = 125 MHz (−7 dBFS ), 128 MHz 25°C 83 83 84 dBc (−7 dBFS) CROSSTALK3 Full −105 −105 −105 −105 dBFS ANALOG INPUT BANDWIDTH 25°C 500 500 500 500 MHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Measurements made with a divide-by-4 clock rate to minimize the effects of clock jitter on the SNR performance. 3 Crosstalk is measured with a 170 MHz tone at −1 dBFS on one channel and no input on the alternate channel. Rev. B | Page 4 of 44 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ADC DC SPECIFICATIONS ADC AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9650-25 AD9650-65 AD9650-80 AD9650-105 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Common-Mode Voltage Servo Dither Large-Signal FFT Small-Signal FFT Static Linearity Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations CHANNEL/CHIP SYNCHRONIZATION POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS SYNC Control (Register 0x100) Bits[7:3]—Reserved Bit 2—Clock Divider Next SYNC Only Bit 1—Clock Divider SYNC Enable Bit 0—Master SYNC Enable APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations LVDS Operation Exposed Paddle Thermal Heat Slug Recommendations VCM RBIAS Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE