Datasheet AD9650 (Analog Devices)

16-Bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) Data Sheet AD9650 FEATURES FUNCTIONAL BLOCK DIAGRAM 1.8 V analog supply operation SDIO/ SCLK/ AVDD CSB DRVDD DCS DFS 1.8 V CMOS or LVDS output supply SNR SPI AD9650 82 dBFS at 30 MHz input and 105 MSPS data rate 83 dBFS at 9.7 MHz input and 25 MSPS data rate PROGRAMMING DATA ORA SFDR VIN+A D15A (MSB) CMOS/LVDS 16 ADC TO 90 dBc at 30 MHz input and 105 MSPS data rate OUTPUT BUFFER VIN–A D0A (LSB) 95 dBc at 9.7 MHz input and 25 MSPS data rate Low power DIVIDE 1 CLK+ VREF TO 8 CLK– 328 mW per channel at 105 MSPS SENSE 119 mW per channel at 25 MSPS DUTY CYCLE DCO DCOA REF STABILIZER GENERATION Integer 1-to-8 input clock divider DCOB VCM SELECT IF sampling frequencies to 300 MHz RBIAS ORB Analog input range of 2.7 V p-p D15B (MSB) VIN–B CMOS/LVDS 16 Optional on-chip dither ADC TO OUTPUT BUFFER VIN+B D0B (LSB) Integrated ADC sample-and-hold inputs MULTICHIP Differential analog inputs with 500 MHz bandwidth SYNC ADC clock duty cycle stabilizer AGND SYNC PDWN OEB APPLICATIONS NOTES 1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY;
001
SEE FIGURE 7 FOR LVDS PIN NAMES. Industrial instrumentation
08919- Figure 1.
X-Ray, MRI, and ultrasound equipment High speed pulse acquisition
Flexible power-down options allow significant power savings,
Chemical and spectrum analysis
when desired.
Direct conversion receivers
Programming for setup and control is accomplished using a 3-wire
Multimode digital receivers
SPI-compatible serial interface.
Smart antenna systems
The AD9650 is available in a 64-lead LFCSP and is specified over
General-purpose software radios
the industrial temperature range of −40°C to +85°C.
GENERAL DESCRIPTION PRODUCT HIGHLIGHTS
The AD9650 is a dual, 16-bit, 25 MSPS/65 MSPS/80 MSPS/ 1. On-chip dither option for improved SFDR performance 105 MSPS analog-to-digital converter (ADC) designed for with low power analog input. digitizing high frequency, wide dynamic range signals with 2. Proprietary differential input that maintains excel ent SNR input frequencies of up to 300 MHz. performance for input frequencies up to 300 MHz. The dual ADC core features a multistage, differential pipelined 3. Operation from a single 1.8 V supply and a separate digital architecture with integrated output error correction logic. Each output driver supply accommodating 1.8 V CMOS or ADC features wide bandwidth, differential sample-and-hold LVDS outputs. analog input amplifiers, and shared integrated voltage reference, 4. Standard serial port interface (SPI) that supports various which eases design considerations. A duty cycle stabilizer is product features and functions, such as data formatting provided to compensate for variations in the ADC clock duty (offset binary, twos complement, or gray coding), enabling cycle, allowing the converters to maintain excellent performance. the clock DCS, power-down, and test modes. The ADC output data can be routed directly to the two external 5. Pin compatible with the AD9268 and other dual families, 16-bit output ports or multiplexed on a single 16-bit bus. These AD9269, AD9251, AD9231, and AD9204. This allows a outputs can be set to either 1.8 V CMOS or LVDS. simple migration across resolutions and bandwidth.
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Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ADC DC SPECIFICATIONS ADC AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9650-25 AD9650-65 AD9650-80 AD9650-105 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Common-Mode Voltage Servo Dither Large-Signal FFT Small-Signal FFT Static Linearity Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations CHANNEL/CHIP SYNCHRONIZATION POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS SYNC Control (Register 0x100) Bits[7:3]—Reserved Bit 2—Clock Divider Next SYNC Only Bit 1—Clock Divider SYNC Enable Bit 0—Master SYNC Enable APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations LVDS Operation Exposed Paddle Thermal Heat Slug Recommendations VCM RBIAS Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE