Datasheet AD9650 (Analog Devices) - 2

AD9650* PRODUCT PAGE QUICK LINKS Last Content Update: 07/01/2017 COMPARABLE PARTS REFERENCE MATERIALS
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Technical Articles
• Improve The Design Of Your Passive Wideband ADC
EVALUATION KITS
Front-End Network • AD9650 Evaluation Board • MS-2210: Designing Power Supplies for High Speed ADC • MS-2677: JESD204B Subclasses - Part 2: Subclass 1 vs.
DOCUMENTATION
Subclass 2 System Considerations
Application Notes DESIGN RESOURCES
• AN-1142: Techniques for High Speed ADC PCB Layout • AD9650 Material Declaration • AN-586: LVDS Outputs for High Speed A/D Converters • PCN-PDN Information • AN-742: Frequency Domain Response of Switched- Capacitor ADCs • Quality And Reliability • AN-807: Multicarrier WCDMA Feasibility • Symbols and Footprints • AN-808: Multicarrier CDMA2000 Feasibility • AN-812: MicroController-Based Serial Port Interface (SPI)
DISCUSSIONS
Boot Circuit View all AD9650 EngineerZone Discussions. • AN-827: A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs
SAMPLE AND BUY
• AN-878: High Speed ADC SPI Control Software Visit the product page to see pricing options.
Data Sheet
• AD9650-EP: Enhanced Product Data Sheet
TECHNICAL SUPPORT
• AD9650: 16-Bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS, 1.8 Submit a technical question or find your regional support V Dual Analog-to-Digital Converter (ADC) Data Sheet number.
User Guides
• UG-003: Evaluating the AD9650/AD9268/AD9258/
DOCUMENT FEEDBACK
AD9251/AD9231/AD9204 Analog-to-Digital Converters Submit feedback for this data sheet.
TOOLS AND SIMULATIONS
• Visual Analog • AD9650 IBIS Model
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Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ADC DC SPECIFICATIONS ADC AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9650-25 AD9650-65 AD9650-80 AD9650-105 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Common-Mode Voltage Servo Dither Large-Signal FFT Small-Signal FFT Static Linearity Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations CHANNEL/CHIP SYNCHRONIZATION POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS SYNC Control (Register 0x100) Bits[7:3]—Reserved Bit 2—Clock Divider Next SYNC Only Bit 1—Clock Divider SYNC Enable Bit 0—Master SYNC Enable APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations LVDS Operation Exposed Paddle Thermal Heat Slug Recommendations VCM RBIAS Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE