Datasheet AD9266 (Analog Devices) - 3
| 制造商 | Analog Devices |
| 描述 | 16-Bit, 20/40/65/80 MSPS, 1.8 V Analog-to-Digital Converter |
| 页数 / 页 | 33 / 3 — AD9266. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY 3/16—Rev. A to … |
| 修订版 | B |
| 文件格式/大小 | PDF / 1.1 Mb |
| 文件语言 | 英语 |
AD9266. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY 3/16—Rev. A to Rev. B. 6/12—Rev. 0 to Rev. A
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AD9266 Data Sheet TABLE OF CONTENTS
Features .. 1 Voltage Reference ... 19 Applications ... 1 Clock Input Considerations .. 20 Functional Block Diagram .. 1 Power Dissipation and Standby Mode .. 22 Product Highlights ... 1 Digital Outputs ... 22 Revision History ... 2 Timing ... 23 General Description ... 3 Output Test .. 24 Specifications ... 4 Output Test Modes ... 24 DC Specifications ... 4 Serial Port Interface (SPI) .. 25 AC Specifications .. 5 Configuration Using the SPI ... 25 Digital Specifications ... 6 Hardware Interface ... 26 Switching Specifications .. 7 Configuration Without the SPI .. 26 Timing Specifications .. 8 SPI Accessible Features .. 26 Absolute Maximum Ratings .. 9 Memory Map .. 27 Thermal Characteristics .. 9 Reading the Memory Map Register Table ... 27 ESD Caution .. 9 Open Locations .. 27 Pin Configuration and Function Descriptions ... 10 Default Values ... 27 Typical Performance Characteristics ... 11 Memory Map Register Table ... 28 AD9266-80 .. 11 Memory Map Register Descriptions .. 30 AD9266-65 .. 13 Applications Information .. 31 AD9266-40 .. 14 Design Guidelines .. 31 AD9266-20 .. 15 Outline Dimensions ... 32 Equivalent Circuits ... 16 Ordering Guide .. 32 Theory of Operation .. 17 Analog Input Considerations .. 17
REVISION HISTORY 3/16—Rev. A to Rev. B
Change to Product Highlights Section .. 1 Changes to Pipeline Delay (Latency) Parameter, Table 4 .. 7 Changes to Figure 3 and Table 8 ... 10 Changes to Clock Input Options Section .. 20 Changes to Data Clock Output Section ... 23
6/12—Rev. 0 to Rev. A
Changes to Table 1 .. 4 Changes to Table 4 .. 7 Changed Built-In Self-Test (BIST) and Output Test Section to Output Test Section .. 24 Changes to Output Test Section; Deleted Built-In Self-Test (BIST) Section ... 24 Changes to Table 16 .. 28
4/10—Revision 0: Initial Version
Rev. B | Page 2 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9266-80 AD9266-65 AD9266-40 AD9266-20 EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations Single-Ended Input Configuration VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) OUTPUT TEST OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE OPEN LOCATIONS DEFAULT VALUES Logic Levels Transfer Register Map MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS USR2 (Register 0x101) Bit 3—Enable GCLK Detect Bit 2—Run GCLK Bit 0—Disable SDIO Pull-Down APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Sink Recommendations VCM RBIAS Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE
AD9266 Data Sheet TABLE OF CONTENTS
Features .. 1 Voltage Reference ... 19 Applications ... 1 Clock Input Considerations .. 20 Functional Block Diagram .. 1 Power Dissipation and Standby Mode .. 22 Product Highlights ... 1 Digital Outputs ... 22 Revision History ... 2 Timing ... 23 General Description ... 3 Output Test .. 24 Specifications ... 4 Output Test Modes ... 24 DC Specifications ... 4 Serial Port Interface (SPI) .. 25 AC Specifications .. 5 Configuration Using the SPI ... 25 Digital Specifications ... 6 Hardware Interface ... 26 Switching Specifications .. 7 Configuration Without the SPI .. 26 Timing Specifications .. 8 SPI Accessible Features .. 26 Absolute Maximum Ratings .. 9 Memory Map .. 27 Thermal Characteristics .. 9 Reading the Memory Map Register Table ... 27 ESD Caution .. 9 Open Locations .. 27 Pin Configuration and Function Descriptions ... 10 Default Values ... 27 Typical Performance Characteristics ... 11 Memory Map Register Table ... 28 AD9266-80 .. 11 Memory Map Register Descriptions .. 30 AD9266-65 .. 13 Applications Information .. 31 AD9266-40 .. 14 Design Guidelines .. 31 AD9266-20 .. 15 Outline Dimensions ... 32 Equivalent Circuits ... 16 Ordering Guide .. 32 Theory of Operation .. 17 Analog Input Considerations .. 17
REVISION HISTORY 3/16—Rev. A to Rev. B
Change to Product Highlights Section .. 1 Changes to Pipeline Delay (Latency) Parameter, Table 4 .. 7 Changes to Figure 3 and Table 8 ... 10 Changes to Clock Input Options Section .. 20 Changes to Data Clock Output Section ... 23
6/12—Rev. 0 to Rev. A
Changes to Table 1 .. 4 Changes to Table 4 .. 7 Changed Built-In Self-Test (BIST) and Output Test Section to Output Test Section .. 24 Changes to Output Test Section; Deleted Built-In Self-Test (BIST) Section ... 24 Changes to Table 16 .. 28
4/10—Revision 0: Initial Version
Rev. B | Page 2 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9266-80 AD9266-65 AD9266-40 AD9266-20 EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations Single-Ended Input Configuration VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) OUTPUT TEST OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE OPEN LOCATIONS DEFAULT VALUES Logic Levels Transfer Register Map MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS USR2 (Register 0x101) Bit 3—Enable GCLK Detect Bit 2—Run GCLK Bit 0—Disable SDIO Pull-Down APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Sink Recommendations VCM RBIAS Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE