Datasheet AD9266 (Analog Devices) - 4

Data Sheet AD9266 GENERAL DESCRIPTION
The AD9266 is a monolithic, single-channel 1.8 V supply, A differential clock input with a selectable internal 1-to-8 divide 16-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital ratio controls all internal conversion cycles. An optional duty cycle converter (ADC). It features a high performance sample-and- stabilizer (DCS) compensates for wide variations in the clock duty hold circuit and on-chip voltage reference. cycle while maintaining excel ent overall ADC performance. The product uses multistage differential pipeline architecture The interleaved digital output data is presented in offset binary, with output error correction logic to provide 16-bit accuracy at gray code, or twos complement format. A DCO is provided to 80 MSPS data rates and to guarantee no missing codes over the ensure proper latch timing with receiving logic. Both 1.8 V and full operating temperature range. 3.3 V CMOS levels are supported. The ADC contains several features designed to maximize The AD9266 is available in a 32-lead RoHS-compliant LFCSP flexibility and minimize system cost, such as programmable and is specified over the industrial temperature range (−40°C clock and data alignment and programmable digital test pattern to +85°C). generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI). Rev. B | Page 3 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9266-80 AD9266-65 AD9266-40 AD9266-20 EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations Single-Ended Input Configuration VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) OUTPUT TEST OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE OPEN LOCATIONS DEFAULT VALUES Logic Levels Transfer Register Map MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS USR2 (Register 0x101) Bit 3—Enable GCLK Detect Bit 2—Run GCLK Bit 0—Disable SDIO Pull-Down APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Sink Recommendations VCM RBIAS Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE