Datasheet AD7195 (Analog Devices) - 6

Data Sheet AD7195 Parameter Min Typ Max Unit Test Conditions/Comments1
LOGIC INPUTS Input High Voltage, V 2 INH 2 V Input Low Voltage, V 2 INL 0.8 V Hysteresis2 0.1 0.25 V Input Currents −10 +10 µA LOGIC OUTPUT (DOUT/RDY) Output High Voltage, V 2 OH DVDD − 0.6 V DVDD = 3 V, ISOURCE = 100 µA Output Low Voltage, V 2 OL 0.4 V DVDD = 3 V, ISINK = 100 µA Output High Voltage, V 2 OH 4 V DVDD = 5 V, ISOURCE = 200 µA Output Low Voltage, V 2 OL 0.4 V DVDD = 5 V, ISINK = 1.6 mA Floating-State Leakage −10 +10 µA Current Floating-State Output 10 pF Capacitance Data Output Coding Offset binary SYSTEM CALIBRATION2 Full-Scale Calibration Limit 1.05 × FS V Zero-Scale Calibration Limit −1.05 × FS V Input Span 0.8 × FS 2.1 × FS V POWER REQUIREMENTS7 Power Supply Voltage AVDD − AGND 4.75 5.25 V DVDD − DGND 2.7 5.25 V Power Supply Currents AIDD Current 0.85 1 mA gain = 1, buffer off 1.1 1.3 mA gain = 1, buffer on 3.5 4.5 mA gain = 8, buffer off 4 5 mA gain = 8, buffer on 5 6.4 mA gain = 16 to 128, buffer off 5.5 6.9 mA gain = 16 to 128, buffer on DIDD Current 0.35 0.4 mA DVDD = 3 V 0.5 0.6 mA DVDD = 5 V 1.5 mA External crystal used IDD (Power-Down Mode) 2 µA 1 Temperature range: −40°C to +105°C. 2 Specification is not production tested, but is supported by characterization data at initial product release. 3 FS is the decimal equivalent of Bit FS9 to Bit FS0 in the mode register. 4 Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed gain and output data rate selected. A system full- scale calibration reduces the gain error to the order of the noise for the programmed gain and output data rate. 5 The analog inputs are configured for differential mode. 6 REJ60 is a bit in the mode register. When the output data rate is set to 50 Hz, setting REJ60 to 1 places a notch at 60 Hz, allowing simultaneous 50 Hz/60 Hz rejection. 7 Digital inputs equal to DVDD or DGND. Rev. A | Page 5 of 44 Document Outline FEATURES INTERFACE APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS Circuit and Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS RMS NOISE AND RESOLUTION SINC4 CHOP DISABLED SINC3 CHOP DISABLED SINC4 CHOP ENABLED SINC3 CHOP ENABLED ON-CHIP REGISTERS COMMUNICATIONS REGISTER STATUS REGISTER MODE REGISTER CONFIGURATION REGISTER DATA REGISTER ID REGISTER GPOCON REGISTER OFFSET REGISTER FULL-SCALE REGISTER ADC CIRCUIT INFORMATION OVERVIEW Analog Inputs Multiplexer PGA Reference Detect Burnout Currents Σ-Δ ADC and Filter AC Excitation Serial Interface Clock Temperature Sensor Calibration ANALOG INPUT CHANNEL PGA REFERENCE REFERENCE DETECT BIPOLAR/UNIPOLAR CONFIGURATION DATA OUTPUT CODING BURNOUT CURRENTS AC EXCITATION CHANNEL SEQUENCER Single Conversion Mode Continuous Conversion Mode Continuous Read RESET SYSTEM SYNCHRONIZATION CLOCK ENABLE PARITY TEMPERATURE SENSOR BRIDGE POWER-DOWN SWITCH CALIBRATION DIGITAL FILTER SINC4 FILTER (CHOP DISABLED) Sinc4 Output Data Rate/Settling Time Sinc4 Zero Latency Sinc4 50 Hz/60 Hz Rejection SINC3 FILTER (CHOP DISABLED) Sinc3 Output Data Rate and Settling Time Sinc3 Zero Latency Sinc3 50 Hz/60 Hz Rejection CHOP ENABLED (SINC4 FILTER) Output Data Rate and Settling Time (Sinc4 Chop Enabled) 50 Hz/60 Hz Rejection (Sinc4 Chop Enabled) CHOP ENABLED (SINC3 FILTER) Output Data Rate and Settling Time (Sinc3 Chop Enabled) 50 Hz/60 Hz Rejection (Sinc3 Chop Enabled) SUMMARY OF FILTER OPTIONS GROUNDING AND LAYOUT APPLICATIONS INFORMATION WEIGH SCALES OUTLINE DIMENSIONS ORDERING GUIDE