Datasheet AD9649 (Analog Devices) - 2

AD9649* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS TOOLS AND SIMULATIONS
View a parametric search of comparable parts. • Visual Analog • AD9649 IBIS Models
EVALUATION KITS
• AD9649 Evaluation Board
REFERENCE MATERIALS Solutions Bulletins & Brochures DOCUMENTATION
• Analog-to-Digital Converter and Drivers ICs Solutions
Application Notes
Bulletin, Volume 10, Issue 2 • AN-1142: Techniques for High Speed ADC PCB Layout
Technical Articles
• AN-586: LVDS Outputs for High Speed A/D Converters • Improve The Design Of Your Passive Wideband ADC Front-End Network • AN-742: Frequency Domain Response of Switched- Capacitor ADCs • MS-2210: Designing Power Supplies for High Speed ADC • AN-807: Multicarrier WCDMA Feasibility • AN-808: Multicarrier CDMA2000 Feasibility
DESIGN RESOURCES
• AN-812: MicroController-Based Serial Port Interface (SPI) • AD9649 Material Declaration Boot Circuit • PCN-PDN Information • AN-827: A Resonant Approach to Interfacing Amplifiers to • Quality And Reliability Switched-Capacitor ADCs • Symbols and Footprints • AN-878: High Speed ADC SPI Control Software • AN-935: Designing an ADC Transformer-Coupled Front
DISCUSSIONS
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Data Sheet
• AD9649: 14-Bit, 20/40/65/80 MSPS, 1.8 V Analog-to-Digital
SAMPLE AND BUY
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User Guides
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SOFTWARE AND SYSTEMS REQUIREMENTS
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Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9649-80 AD9649-65 AD9649-40 AD9649-20 EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations Single-Ended Input Configuration VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE OPEN LOCATIONS DEFAULT VALUES Logic Levels Transfer Register Map MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS USR2 (Register 0x101) Bit 3—Enable GCLK Detect Bit 2—Run GCLK Bit 0—Disable SDIO Pull-Down APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Sink Recommendations Encode Clock VCM RBIAS Reference Decoupling SPI Port Soft Reset OUTLINE DIMENSIONS ORDERING GUIDE