Datasheet AD7626 (Analog Devices) - 7
| 制造商 | Analog Devices |
| 描述 | 16-Bit, 10 MSPS, PulSAR Differential ADC |
| 页数 / 页 | 30 / 7 — AD7626. Data Sheet. TIMING SPECIFICATIONS. Table 3. Parameter. Symbol. … |
| 修订版 | D |
| 文件格式/大小 | PDF / 1.0 Mb |
| 文件语言 | 英语 |
AD7626. Data Sheet. TIMING SPECIFICATIONS. Table 3. Parameter. Symbol. Min. Typ. Max. Unit
该数据表的模型线
文件文字版本
AD7626 Data Sheet TIMING SPECIFICATIONS
VDD1 = 5 V; VDD2 = 2.5 V; VIO = 2.37 V to 2.63 V; REF = 4.096 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3. Parameter Symbol Min Typ Max Unit
Time Between Conversions1 tCYC 100 10,000 ns Acquisition Time tACQ 40 ns CNV High Time tCNVH 10 40 ns CNV to D (MSB) Ready tMSB 100 ns CNV to Last CLK (LSB) Delay tCLKL 72 ns CLK Period2 tCLK 3.33 4 (tCYC − tMSB + tCLKL)/n ns CLK Frequency fCLK 250 300 MHz CLK to DCO Delay (Echoed Clock Mode) tDCO 0 4 7 ns DCO to D Delay (Echoed Clock Mode) tD 0 1 ns CLK to D Delay tCLKD 0 4 7 ns 1 The maximum time between conversions is 10,000 ns. If CNV± is left idle for a time greater than the maximum value of tCYC, the subsequent conversion result is invalid. 2 For the maximum CLK period, the window available to read data is tCYC − tMSB + tCLKL. Divide this time by the number of bits (n) to be read giving the maximum CLK± frequency that can be used for a given conversion CNV frequency. In echoed clock interface mode, n = 16; in self clocked interface mode, n = 18. Rev. D | Page 6 of 29 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER INFORMATION TRANSFER FUNCTIONS ANALOG INPUTS TYPICAL CONNECTION DIAGRAM DRIVING THE AD7626 Differential Analog Input Source Single-Ended to Differential Driver Single-Ended or Fully Differential High Frequency Driver VOLTAGE REFERENCE OPTIONS Wake-Up Time from EN1 = 0, EN0 = 0 POWER SUPPLY Power-Up DIGITAL INTERFACE Conversion Control Echoed Clock Interface Mode Self Clocked Mode APPLICATIONS INFORMATION LAYOUT, DECOUPLING, AND GROUNDING Exposed Paddle VDD1 Supply Routing and Decoupling VIO Supply Decoupling Layout and Decoupling of Pin 25 to Pin 32 OUTLINE DIMENSIONS ORDERING GUIDE
VDD1 = 5 V; VDD2 = 2.5 V; VIO = 2.37 V to 2.63 V; REF = 4.096 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3. Parameter Symbol Min Typ Max Unit
Time Between Conversions1 tCYC 100 10,000 ns Acquisition Time tACQ 40 ns CNV High Time tCNVH 10 40 ns CNV to D (MSB) Ready tMSB 100 ns CNV to Last CLK (LSB) Delay tCLKL 72 ns CLK Period2 tCLK 3.33 4 (tCYC − tMSB + tCLKL)/n ns CLK Frequency fCLK 250 300 MHz CLK to DCO Delay (Echoed Clock Mode) tDCO 0 4 7 ns DCO to D Delay (Echoed Clock Mode) tD 0 1 ns CLK to D Delay tCLKD 0 4 7 ns 1 The maximum time between conversions is 10,000 ns. If CNV± is left idle for a time greater than the maximum value of tCYC, the subsequent conversion result is invalid. 2 For the maximum CLK period, the window available to read data is tCYC − tMSB + tCLKL. Divide this time by the number of bits (n) to be read giving the maximum CLK± frequency that can be used for a given conversion CNV frequency. In echoed clock interface mode, n = 16; in self clocked interface mode, n = 18. Rev. D | Page 6 of 29 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER INFORMATION TRANSFER FUNCTIONS ANALOG INPUTS TYPICAL CONNECTION DIAGRAM DRIVING THE AD7626 Differential Analog Input Source Single-Ended to Differential Driver Single-Ended or Fully Differential High Frequency Driver VOLTAGE REFERENCE OPTIONS Wake-Up Time from EN1 = 0, EN0 = 0 POWER SUPPLY Power-Up DIGITAL INTERFACE Conversion Control Echoed Clock Interface Mode Self Clocked Mode APPLICATIONS INFORMATION LAYOUT, DECOUPLING, AND GROUNDING Exposed Paddle VDD1 Supply Routing and Decoupling VIO Supply Decoupling Layout and Decoupling of Pin 25 to Pin 32 OUTLINE DIMENSIONS ORDERING GUIDE