Datasheet AD7194 (Analog Devices) - 4
| 制造商 | Analog Devices |
| 描述 | 8-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA |
| 页数 / 页 | 55 / 4 — Data Sheet. AD7194. SPECIFICATIONS. Table 1. Parameter. Min. Typ. Max. … |
| 修订版 | B |
| 文件格式/大小 | PDF / 1.1 Mb |
| 文件语言 | 英语 |
Data Sheet. AD7194. SPECIFICATIONS. Table 1. Parameter. Min. Typ. Max. Unit. Test Conditions/Comments1
该数据表的模型线
文件文字版本
link to page 7 link to page 16 link to page 16 link to page 7 link to page 39 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7
Data Sheet AD7194 SPECIFICATIONS
AVDD = 3 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V; REFINx(+) = +2.5 V or AVDD, REFINx(−) = AGND, MCLK = 4.92 MHz, TA = TMIN to TMAX, unless otherwise noted.
Table 1. Parameter Min Typ Max Unit Test Conditions/Comments1
ADC Output Data Rate 4.7 4800 Hz Chop disabled 1.17 1200 Hz Chop enabled, sinc4 filter 1.56 1600 Hz Chop enabled, sinc3 filter No Missing Codes2 24 Bits FS[9:0]3 > 1, sinc4 filter 24 Bits FS[9:0]3 > 4, sinc3 filter Resolution See the RMS Noise and Resolution section RMS Noise and Output See the RMS Noise and Resolution section Data Rates Integral Nonlinearity Gain = 12 ±2 ±10 ppm of FSR AVDD = 5 V ±2 ±15 ppm of FSR AVDD = 3 V Gain > 1 ±5 ±30 ppm of FSR AVDD = 5 V ±15 ±30 ppm of FSR AVDD = 3 V Offset Error4, 5 ±150/gain µV Chop disabled ±1 µV Chop enabled, AVDD = 5 V ±0.5 µV Chop enabled, AVDD = 3 V Offset Error Drift vs. ±150/gain nV/°C Gain = 1 to 16; chop disabled Temperature ±5 nV/°C Gain = 32 to 128; chop disabled ±5 nV/°C Chop enabled Gain Error4 ±0.001 % AVDD = 5 V, gain = 1, TA = 25°C (factory calibration conditions) −0.4 % Gain = 128, before full-scale calibration (see Table 27) ±0.003 % Gain > 1, after internal ful -scale calibration, AVDD ≥ 4.75 V ±0.005 % Gain > 1, after internal ful -scale calibration, AVDD < 4.75 V Gain Drift vs. ±1 ppm/°C Temperature Power Supply Rejection 90 dB Gain = 1, VIN = 1 V 95 110 dB Gain > 1, VIN = 1 V/gain Common-Mode Rejection @ DC 110 dB Gain = 1, VIN = 1 V @ DC 105 120 dB Gain > 1, VIN = 1 V/gain @ 50 Hz, 60 Hz2 120 dB 10 Hz output data rate, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz @ 50 Hz2 120 dB 50 Hz output data rate, 50 Hz ± 1 Hz @ 60 Hz2 120 dB 60 Hz output data rate, 60 Hz ± 1 Hz @ 50 Hz2 115 dB Fast settling, FS[9:0]3 = 6, average by 16, 50 Hz ± 1 Hz @ 60 Hz2 115 dB Fast settling, FS[9:0]3 = 5, average by 16, 60 Hz ± 1 Hz Rev. B | Page 3 of 54 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS Circuit and Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS RMS NOISE AND RESOLUTION SINC4 CHOP DISABLED SINC3 CHOP DISABLED FAST SETTLING ON-CHIP REGISTERS COMMUNICATIONS REGISTER RS2, RS1, RS0 = 000 STATUS REGISTER RS2, RS1, RS0 = 000; Power-On/Reset = 0x80 MODE REGISTER RS2, RS1, RS0 = 001; Power-On/Reset = 0x080060 CONFIGURATION REGISTER RS2, RS1, RS0 = 010; Power-On/Reset = 0x000117 Channel Selection (Pseudo Bit = 0) DATA REGISTER RS2, RS1, RS0 = 011; Power-On/Reset = 0x000000 ID REGISTER RS2, RS1, RS0 = 100; Power-On/Reset = 0xX3 GPOCON REGISTER RS2, RS1, RS0 = 101; Power-On/Reset = 0x00 OFFSET REGISTER RS2, RS1, RS0 = 110; Power-On/Reset = 0x800000) FULL-SCALE REGISTER RS2, RS1, RS0 = 111; Power-On/Reset = 0x5XXXX0 ADC CIRCUIT INFORMATION OVERVIEW Analog Inputs Multiplexer PGA Reference Detect Burnout Currents Σ-Δ ADC and Filter Serial Interface Clock Temperature Sensor Digital Outputs Calibration ANALOG INPUT CHANNEL PROGRAMMABLE GAIN ARRAY (PGA) REFERENCE REFERENCE DETECT BIPOLAR/UNIPOLAR CONFIGURATION DATA OUTPUT CODING BURNOUT CURRENTS DIGITAL INTERFACE Single Conversion Mode Continuous Conversion Mode Continuous Read RESET SYSTEM SYNCHRONIZATION ENABLE PARITY CLOCK TEMPERATURE SENSOR LOGIC OUTPUTS CALIBRATION DIGITAL FILTER SINC4 FILTER (CHOP DISABLED) Sinc4 Output Data Rate/Settling Time Sinc4 Zero Latency Sinc4 50 Hz/60 Hz Rejection SINC3 FILTER (CHOP DISABLED) Sinc3 Output Data Rate and Settling Time Sinc3 Zero Latency Sinc3 50 Hz/60 Hz Rejection CHOP ENABLED (SINC4 FILTER) Output Data Rate and Settling Time (Sinc4 Chop Enabled) 50 Hz/60 Hz Rejection (Sinc4 Chop Enabled) CHOP ENABLED (SINC3 FILTER) Output Data Rate and Settling Time (Sinc3 Chop Enabled) 50 Hz/60 Hz Rejection (Sinc3 Chop Enabled) FAST SETTLING MODE (SINC4 FILTER) Output Data Rate and Settling Time, Sinc4 Filter 50 Hz/60 Hz Rejection, Sinc4 Filter FAST SETTLING MODE (SINC3 FILTER) Output Data Rate and Settling Time, Sinc3 Filter 50 Hz/60 Hz Rejection, Sinc3 Filter FAST SETTLING MODE (CHOP ENABLED) SUMMARY OF FILTER OPTIONS GROUNDING AND LAYOUT APPLICATIONS INFORMATION FLOWMETER OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet AD7194 SPECIFICATIONS
AVDD = 3 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V; REFINx(+) = +2.5 V or AVDD, REFINx(−) = AGND, MCLK = 4.92 MHz, TA = TMIN to TMAX, unless otherwise noted.
Table 1. Parameter Min Typ Max Unit Test Conditions/Comments1
ADC Output Data Rate 4.7 4800 Hz Chop disabled 1.17 1200 Hz Chop enabled, sinc4 filter 1.56 1600 Hz Chop enabled, sinc3 filter No Missing Codes2 24 Bits FS[9:0]3 > 1, sinc4 filter 24 Bits FS[9:0]3 > 4, sinc3 filter Resolution See the RMS Noise and Resolution section RMS Noise and Output See the RMS Noise and Resolution section Data Rates Integral Nonlinearity Gain = 12 ±2 ±10 ppm of FSR AVDD = 5 V ±2 ±15 ppm of FSR AVDD = 3 V Gain > 1 ±5 ±30 ppm of FSR AVDD = 5 V ±15 ±30 ppm of FSR AVDD = 3 V Offset Error4, 5 ±150/gain µV Chop disabled ±1 µV Chop enabled, AVDD = 5 V ±0.5 µV Chop enabled, AVDD = 3 V Offset Error Drift vs. ±150/gain nV/°C Gain = 1 to 16; chop disabled Temperature ±5 nV/°C Gain = 32 to 128; chop disabled ±5 nV/°C Chop enabled Gain Error4 ±0.001 % AVDD = 5 V, gain = 1, TA = 25°C (factory calibration conditions) −0.4 % Gain = 128, before full-scale calibration (see Table 27) ±0.003 % Gain > 1, after internal ful -scale calibration, AVDD ≥ 4.75 V ±0.005 % Gain > 1, after internal ful -scale calibration, AVDD < 4.75 V Gain Drift vs. ±1 ppm/°C Temperature Power Supply Rejection 90 dB Gain = 1, VIN = 1 V 95 110 dB Gain > 1, VIN = 1 V/gain Common-Mode Rejection @ DC 110 dB Gain = 1, VIN = 1 V @ DC 105 120 dB Gain > 1, VIN = 1 V/gain @ 50 Hz, 60 Hz2 120 dB 10 Hz output data rate, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz @ 50 Hz2 120 dB 50 Hz output data rate, 50 Hz ± 1 Hz @ 60 Hz2 120 dB 60 Hz output data rate, 60 Hz ± 1 Hz @ 50 Hz2 115 dB Fast settling, FS[9:0]3 = 6, average by 16, 50 Hz ± 1 Hz @ 60 Hz2 115 dB Fast settling, FS[9:0]3 = 5, average by 16, 60 Hz ± 1 Hz Rev. B | Page 3 of 54 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS Circuit and Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS RMS NOISE AND RESOLUTION SINC4 CHOP DISABLED SINC3 CHOP DISABLED FAST SETTLING ON-CHIP REGISTERS COMMUNICATIONS REGISTER RS2, RS1, RS0 = 000 STATUS REGISTER RS2, RS1, RS0 = 000; Power-On/Reset = 0x80 MODE REGISTER RS2, RS1, RS0 = 001; Power-On/Reset = 0x080060 CONFIGURATION REGISTER RS2, RS1, RS0 = 010; Power-On/Reset = 0x000117 Channel Selection (Pseudo Bit = 0) DATA REGISTER RS2, RS1, RS0 = 011; Power-On/Reset = 0x000000 ID REGISTER RS2, RS1, RS0 = 100; Power-On/Reset = 0xX3 GPOCON REGISTER RS2, RS1, RS0 = 101; Power-On/Reset = 0x00 OFFSET REGISTER RS2, RS1, RS0 = 110; Power-On/Reset = 0x800000) FULL-SCALE REGISTER RS2, RS1, RS0 = 111; Power-On/Reset = 0x5XXXX0 ADC CIRCUIT INFORMATION OVERVIEW Analog Inputs Multiplexer PGA Reference Detect Burnout Currents Σ-Δ ADC and Filter Serial Interface Clock Temperature Sensor Digital Outputs Calibration ANALOG INPUT CHANNEL PROGRAMMABLE GAIN ARRAY (PGA) REFERENCE REFERENCE DETECT BIPOLAR/UNIPOLAR CONFIGURATION DATA OUTPUT CODING BURNOUT CURRENTS DIGITAL INTERFACE Single Conversion Mode Continuous Conversion Mode Continuous Read RESET SYSTEM SYNCHRONIZATION ENABLE PARITY CLOCK TEMPERATURE SENSOR LOGIC OUTPUTS CALIBRATION DIGITAL FILTER SINC4 FILTER (CHOP DISABLED) Sinc4 Output Data Rate/Settling Time Sinc4 Zero Latency Sinc4 50 Hz/60 Hz Rejection SINC3 FILTER (CHOP DISABLED) Sinc3 Output Data Rate and Settling Time Sinc3 Zero Latency Sinc3 50 Hz/60 Hz Rejection CHOP ENABLED (SINC4 FILTER) Output Data Rate and Settling Time (Sinc4 Chop Enabled) 50 Hz/60 Hz Rejection (Sinc4 Chop Enabled) CHOP ENABLED (SINC3 FILTER) Output Data Rate and Settling Time (Sinc3 Chop Enabled) 50 Hz/60 Hz Rejection (Sinc3 Chop Enabled) FAST SETTLING MODE (SINC4 FILTER) Output Data Rate and Settling Time, Sinc4 Filter 50 Hz/60 Hz Rejection, Sinc4 Filter FAST SETTLING MODE (SINC3 FILTER) Output Data Rate and Settling Time, Sinc3 Filter 50 Hz/60 Hz Rejection, Sinc3 Filter FAST SETTLING MODE (CHOP ENABLED) SUMMARY OF FILTER OPTIONS GROUNDING AND LAYOUT APPLICATIONS INFORMATION FLOWMETER OUTLINE DIMENSIONS ORDERING GUIDE