Datasheet AD9267 (Analog Devices) - 6

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AD9267 DIGITAL SPECIFICATIONS
All power supplies set to 1.8 V, 640 MHz sample rate, 2 V p-p differential input, 0.5 V internal reference, PLL disabled, AIN = −2.0 dBFS, unless otherwise noted.
Table 3. Parameter Temp Min Typ Max Unit
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS1/LVDS/LVPECL Differential Input Voltage Full 0.4 0.8 2 V p-p Input Common-Mode Range Full 450 mV High Level Input Current Full −60 +60 μA Low Level Input Current Full −60 +60 μA Input Resistance Full 20 kΩ diff Input Capacitance Full 1 pF LOGIC INPUTS (SCLK) High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −50 −75 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 30 kΩ Input Capacitance Full 2 pF LOGIC INPUTS (SDIO, CSB, RESET) High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −10 +10 μA Low Level Input Current Full +40 +135 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF DIGITAL OUTPUTS (D0±x to D3±x) ANSI-644 Logic Compliance LVDS Differential Output Voltage (VOD) Full 247 454 mV Output Offset Voltage (VOS) Full 1.125 1.375 V Output Coding (Default) Twos complement Low Power, Reduced Signal Option Logic Compliance LVDS Differential Output Voltage (VOD) Full 150 250 mV Output Offset Voltage (VOS) Full 1.10 1.30 V Output Coding (Default) Twos complement 1 For voltage swings beyond the specified range, clamping diodes are recommended. Rev. 0 | Page 5 of 24 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Direct Clocking Internal PLL Clock Distribution External PLL Control PLL Autoband Select Power Dissipation and Standby Mode Digital Outputs Digital Output Format Overrange (OR) Condition Timing Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Applications Information Filtering Requirement Memory Map Memory Map Definitions Outline Dimensions Ordering Guide