Datasheet AD9251 (Analog Devices) - 2

AD9251* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS REFERENCE MATERIALS
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Product Selection Guide
• RF Source Booklet
EVALUATION KITS Technical Articles
• AD9251 Evaluation Board • Designing 1-ppm DAC Accuracy into Instrumentation Applications - Part 1
DOCUMENTATION
• Designing 1-ppm DAC Accuracy into Instrumentation
Application Notes
Applications - Part 2 • AN-1142: Techniques for High Speed ADC PCB Layout • Improve The Design Of Your Passive Wideband ADC Front-End Network • AN-742: Frequency Domain Response of Switched- Capacitor ADCs • MS-2210: Designing Power Supplies for High Speed ADC • AN-807: Multicarrier WCDMA Feasibility
DESIGN RESOURCES
• AN-808: Multicarrier CDMA2000 Feasibility • AD9251 Material Declaration • AN-812: MicroController-Based Serial Port Interface (SPI) Boot Circuit • PCN-PDN Information • AN-827: A Resonant Approach to Interfacing Amplifiers to • Quality And Reliability Switched-Capacitor ADCs • Symbols and Footprints • AN-878: High Speed ADC SPI Control Software • AN-905: Visual Analog Converter Evaluation Tool Version
DISCUSSIONS
1.0 User Manual View all AD9251 EngineerZone Discussions. • AN-935: Designing an ADC Transformer-Coupled Front End
SAMPLE AND BUY Data Sheet
Visit the product page to see pricing options. • AD9251: 14-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converter Data Sheet
TECHNICAL SUPPORT User Guides
Submit a technical question or find your regional support • UG-003: Evaluating the AD9650/AD9268/AD9258/ number. AD9251/AD9231/AD9204 Analog-to-Digital Converters
DOCUMENT FEEDBACK TOOLS AND SIMULATIONS
Submit feedback for this data sheet. • Visual Analog • AD9251 IBIS Models • AD9204/AD9231/AD9251 S-Parameter Data
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Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9251-80 AD9251-65 AD9251-40 AD9251-20 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations Single-Ended Input Configuration VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations CHANNEL/CHIP SYNCHRONIZATION POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE OPEN LOCATIONS DEFAULT VALUES Logic Levels Transfer Register Map Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Sync Control (Register 0x100) Bits[7:3]—Reserved Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Enable Bit 7—Enable OEB Pin 47 Bit 3—Enable GCLK Detect Bit 2—Run GCLK Bit 0—Disable SDIO Pull-Down APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Sink Recommendations VCM RBIAS Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE