Datasheet AD9251 (Analog Devices) - 3
| 制造商 | Analog Devices |
| 描述 | 14-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converter |
| 页数 / 页 | 37 / 3 — AD9251. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY 9/2016—Rev. A to … |
| 修订版 | B |
| 文件格式/大小 | PDF / 1.1 Mb |
| 文件语言 | 英语 |
AD9251. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY 9/2016—Rev. A to Rev. B. 10/2009—Rev. 0 to Rev. A
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AD9251 Data Sheet TABLE OF CONTENTS
Features .. 1 Voltage Reference ... 23 Applications ... 1 Clock Input Considerations .. 24 Functional Block Diagram .. 1 Channel/Chip Synchronization .. 26 Product Highlights ... 1 Power Dissipation and Standby Mode .. 26 Revision History ... 2 Digital Outputs ... 27 General Description ... 3 Timing.. 27 Specifications ... 4 Built-In Self-Test (BIST) and Output Test .. 28 DC Specifications ... 4 Built-In Self-Test (BIST) .. 28 AC Specifications .. 5 Output Test Modes ... 28 Digital Specifications ... 6 Serial Port Interface (SPI) .. 29 Switching Specifications .. 7 Configuration Using the SPI ... 29 Timing Specifications .. 8 Hardware Interface ... 30 Absolute Maximum Ratings .. 10 Configuration Without the SPI .. 30 Thermal Characteristics .. 10 SPI Accessible Features .. 30 ESD Caution .. 10 Memory Map .. 31 Pin Configuration and Function Descriptions ... 11 Reading the Memory Map Register Table ... 31 Typical Performance Characteristics ... 13 Open Locations .. 31 AD9251-80 .. 13 Default Values ... 31 AD9251-65 .. 15 Memory Map Register Table ... 32 AD9251-40 .. 16 Memory Map Register Descriptions .. 34 AD9251-20 .. 17 Applications Information .. 35 Equivalent Circuits ... 18 Design Guidelines .. 35 Theory of Operation .. 20 Outline Dimensions ... 36 ADC Architecture .. 20 Ordering Guide .. 36 Analog Input Considerations .. 20
REVISION HISTORY 9/2016—Rev. A to Rev. B
Changes to Internal Reference Connection Section .. 23 Changes to Figure 3 .. 8 Moved Channel/Chip Synchronization Section ... 26 Change to Table 15 ... 30
10/2009—Rev. 0 to Rev. A
Changes to Reading the Memory Map Register Changes to Features .. 1 Table Section ... 31 Change to Table 1 ... 4 Changes to Table 16 ... 32 Moved Timing Diagrams... 8 Deleted Table 11; Renumbered Sequentially .. 22
7/2009—Revision 0: Initial Version
Rev. B | Page 2 of 36 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9251-80 AD9251-65 AD9251-40 AD9251-20 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations Single-Ended Input Configuration VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations CHANNEL/CHIP SYNCHRONIZATION POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE OPEN LOCATIONS DEFAULT VALUES Logic Levels Transfer Register Map Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Sync Control (Register 0x100) Bits[7:3]—Reserved Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Enable Bit 7—Enable OEB Pin 47 Bit 3—Enable GCLK Detect Bit 2—Run GCLK Bit 0—Disable SDIO Pull-Down APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Sink Recommendations VCM RBIAS Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE
AD9251 Data Sheet TABLE OF CONTENTS
Features .. 1 Voltage Reference ... 23 Applications ... 1 Clock Input Considerations .. 24 Functional Block Diagram .. 1 Channel/Chip Synchronization .. 26 Product Highlights ... 1 Power Dissipation and Standby Mode .. 26 Revision History ... 2 Digital Outputs ... 27 General Description ... 3 Timing.. 27 Specifications ... 4 Built-In Self-Test (BIST) and Output Test .. 28 DC Specifications ... 4 Built-In Self-Test (BIST) .. 28 AC Specifications .. 5 Output Test Modes ... 28 Digital Specifications ... 6 Serial Port Interface (SPI) .. 29 Switching Specifications .. 7 Configuration Using the SPI ... 29 Timing Specifications .. 8 Hardware Interface ... 30 Absolute Maximum Ratings .. 10 Configuration Without the SPI .. 30 Thermal Characteristics .. 10 SPI Accessible Features .. 30 ESD Caution .. 10 Memory Map .. 31 Pin Configuration and Function Descriptions ... 11 Reading the Memory Map Register Table ... 31 Typical Performance Characteristics ... 13 Open Locations .. 31 AD9251-80 .. 13 Default Values ... 31 AD9251-65 .. 15 Memory Map Register Table ... 32 AD9251-40 .. 16 Memory Map Register Descriptions .. 34 AD9251-20 .. 17 Applications Information .. 35 Equivalent Circuits ... 18 Design Guidelines .. 35 Theory of Operation .. 20 Outline Dimensions ... 36 ADC Architecture .. 20 Ordering Guide .. 36 Analog Input Considerations .. 20
REVISION HISTORY 9/2016—Rev. A to Rev. B
Changes to Internal Reference Connection Section .. 23 Changes to Figure 3 .. 8 Moved Channel/Chip Synchronization Section ... 26 Change to Table 15 ... 30
10/2009—Rev. 0 to Rev. A
Changes to Reading the Memory Map Register Changes to Features .. 1 Table Section ... 31 Change to Table 1 ... 4 Changes to Table 16 ... 32 Moved Timing Diagrams... 8 Deleted Table 11; Renumbered Sequentially .. 22
7/2009—Revision 0: Initial Version
Rev. B | Page 2 of 36 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9251-80 AD9251-65 AD9251-40 AD9251-20 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations Single-Ended Input Configuration VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations CHANNEL/CHIP SYNCHRONIZATION POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE OPEN LOCATIONS DEFAULT VALUES Logic Levels Transfer Register Map Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Sync Control (Register 0x100) Bits[7:3]—Reserved Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Enable Bit 7—Enable OEB Pin 47 Bit 3—Enable GCLK Detect Bit 2—Run GCLK Bit 0—Disable SDIO Pull-Down APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Sink Recommendations VCM RBIAS Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE