Datasheet AD9230-11 (Analog Devices) - 9
| 制造商 | Analog Devices |
| 描述 | 11-Bit, 200 MSPS, 1.8 V Analog-to-Digital Converter |
| 页数 / 页 | 29 / 9 — AD9230-11. ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating. THERMAL … |
| 文件格式/大小 | PDF / 665 Kb |
| 文件语言 | 英语 |
AD9230-11. ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating. THERMAL RESISTANCE. Table 6. Package Type. θJA. θJC Unit. ESD CAUTION
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AD9230-11 ABSOLUTE MAXIMUM RATINGS Table 5.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress
Parameter Rating
rating only; functional operation of the device at these or any Electrical other conditions above those indicated in the operational AVDD to AGND −0.3 V to +2.0 V section of this specification is not implied. Exposure to absolute DRVDD to DRGND −0.3 V to +2.0 V maximum rating conditions for extended periods may affect AGND to DRGND −0.3 V to +0.3 V device reliability. AVDD to DRVDD −2.0 V to +2.0 V D0+/D0− through D10+/D10− −0.3 V to DRVDD + 0.3 V
THERMAL RESISTANCE
to DRGND The exposed paddle must be soldered to the ground plane DCO+/DCO− to DRGND −0.3 V to DRVDD + 0.3 V for the LFCSP package. Soldering the exposed paddle to the OR+/OR− to DGND −0.3 V to DRVDD + 0.3 V customer board increases the reliability of the solder joints, CLK+ to AGND −0.3 V to +3.9 V maximizing the thermal capability of the package. CLK− to AGND −0.3 V to +3.9 V VIN+ to AGND −0.3 V to AVDD + 0.2 V
Table 6.
VIN− to AGND −0.3 V to AVDD + 0.2 V
Package Type θJA θJC Unit
SDIO/DCS to DGND −0.3 V to DRVDD + 0.3 V 56-Lead LFCSP (CP-56-2) 30.4 2.9 °C/W PWDN to AGND −0.3 V to +3.9 V Typical θJA and θJC are specified for a 4-layer board in still air. CSB to AGND −0.3 V to +3.9 V Airflow increases heat dissipation, effectively reducing θJA. In SCLK/DFS to AGND −0.3 V to +3.9 V addition, metal that is in direct contact with the package leads Environmental reduces the θJA. Storage Temperature Range −65°C to +125°C Operating Temperature Range −40°C to +85°C
ESD CAUTION
Lead Temperature 300°C (Soldering, 10 sec) Junction Temperature 150°C Rev. 0 | Page 8 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE Differential Input Configurations CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS Digital Outputs and Timing Output Data Rate and Pinout Configuration Out-of-Range (OR) TIMING RBIAS CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS TRANSFER REGISTER MAP OUTLINE DIMENSIONS ORDERING GUIDE
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress
Parameter Rating
rating only; functional operation of the device at these or any Electrical other conditions above those indicated in the operational AVDD to AGND −0.3 V to +2.0 V section of this specification is not implied. Exposure to absolute DRVDD to DRGND −0.3 V to +2.0 V maximum rating conditions for extended periods may affect AGND to DRGND −0.3 V to +0.3 V device reliability. AVDD to DRVDD −2.0 V to +2.0 V D0+/D0− through D10+/D10− −0.3 V to DRVDD + 0.3 V
THERMAL RESISTANCE
to DRGND The exposed paddle must be soldered to the ground plane DCO+/DCO− to DRGND −0.3 V to DRVDD + 0.3 V for the LFCSP package. Soldering the exposed paddle to the OR+/OR− to DGND −0.3 V to DRVDD + 0.3 V customer board increases the reliability of the solder joints, CLK+ to AGND −0.3 V to +3.9 V maximizing the thermal capability of the package. CLK− to AGND −0.3 V to +3.9 V VIN+ to AGND −0.3 V to AVDD + 0.2 V
Table 6.
VIN− to AGND −0.3 V to AVDD + 0.2 V
Package Type θJA θJC Unit
SDIO/DCS to DGND −0.3 V to DRVDD + 0.3 V 56-Lead LFCSP (CP-56-2) 30.4 2.9 °C/W PWDN to AGND −0.3 V to +3.9 V Typical θJA and θJC are specified for a 4-layer board in still air. CSB to AGND −0.3 V to +3.9 V Airflow increases heat dissipation, effectively reducing θJA. In SCLK/DFS to AGND −0.3 V to +3.9 V addition, metal that is in direct contact with the package leads Environmental reduces the θJA. Storage Temperature Range −65°C to +125°C Operating Temperature Range −40°C to +85°C
ESD CAUTION
Lead Temperature 300°C (Soldering, 10 sec) Junction Temperature 150°C Rev. 0 | Page 8 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE Differential Input Configurations CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS Digital Outputs and Timing Output Data Rate and Pinout Configuration Out-of-Range (OR) TIMING RBIAS CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS TRANSFER REGISTER MAP OUTLINE DIMENSIONS ORDERING GUIDE