Datasheet AD9601 (Analog Devices) - 5
| 制造商 | Analog Devices |
| 描述 | 10-Bit, 200 MSPS/250 MSPS 1.8 V Analog-to-Digital Converter |
| 页数 / 页 | 33 / 5 — AD9601. AC SPECIFICATIONS. Table 2. AD9601-200. AD9601-250. Parameter2. … |
| 文件格式/大小 | PDF / 989 Kb |
| 文件语言 | 英语 |
AD9601. AC SPECIFICATIONS. Table 2. AD9601-200. AD9601-250. Parameter2. Temp. Min. Typ. Max. Unit
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AD9601 AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted. 1
Table 2. AD9601-200 AD9601-250 Parameter2 Temp Min Typ Max Min Typ Max Unit
SNR fIN = 10 MHz 25°C 59.5 59.4 dB Full 58.5 57.8 dB fIN = 70 MHz 25°C 59.3 59.4 dB SINAD fIN = 10 MHz 25°C 59.5 59.4 dB Full 58.5 57.7 dB fIN = 70 MHz 25°C 59.3 59.4 dB EFFECTIVE NUMBER OF BITS (ENOB) fIN = 10 MHz 25°C 9.6 9.7 Bits fIN = 70 MHz 25°C 9.6 9.7 Bits WORST HARMONIC (SECOND OR THIRD) fIN = 10 MHz 25°C 84 84 dBc Full 77 72 dBc fIN = 70 MHz 25°C 78 81 dBc WORST OTHER (SFDR EXCLUDING SECOND AND THIRD) fIN = 10 MHz 25°C 88 86 dBc Full 80 75 dBc fIN = 70 MHz 25°C 87 85 dBc TWO-TONE IMD 170.2 MHz/171.3 MHz @ −7 dBFS 25°C 81 81 dBFS ANALOG INPUT BANDWIDTH 25°C 700 700 MHz 1 All ac specifications tested by driving CLK+ and CLK− differentially. 2 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. Rev. 0 | Page 4 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE Differential Input Configurations CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS Digital Outputs and Timing Out-of-Range TIMING—SINGLE PORT MODE TIMING—INTERLEAVED MODE fS/2 Spurious LAYOUT CONSIDERATIONS POWER AND GROUND RECOMMENDATIONS Exposed Paddle Thermal Heat Slug Recommendations CML RBIAS AD9601 CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE
AD9601 AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted. 1
Table 2. AD9601-200 AD9601-250 Parameter2 Temp Min Typ Max Min Typ Max Unit
SNR fIN = 10 MHz 25°C 59.5 59.4 dB Full 58.5 57.8 dB fIN = 70 MHz 25°C 59.3 59.4 dB SINAD fIN = 10 MHz 25°C 59.5 59.4 dB Full 58.5 57.7 dB fIN = 70 MHz 25°C 59.3 59.4 dB EFFECTIVE NUMBER OF BITS (ENOB) fIN = 10 MHz 25°C 9.6 9.7 Bits fIN = 70 MHz 25°C 9.6 9.7 Bits WORST HARMONIC (SECOND OR THIRD) fIN = 10 MHz 25°C 84 84 dBc Full 77 72 dBc fIN = 70 MHz 25°C 78 81 dBc WORST OTHER (SFDR EXCLUDING SECOND AND THIRD) fIN = 10 MHz 25°C 88 86 dBc Full 80 75 dBc fIN = 70 MHz 25°C 87 85 dBc TWO-TONE IMD 170.2 MHz/171.3 MHz @ −7 dBFS 25°C 81 81 dBFS ANALOG INPUT BANDWIDTH 25°C 700 700 MHz 1 All ac specifications tested by driving CLK+ and CLK− differentially. 2 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. Rev. 0 | Page 4 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE Differential Input Configurations CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS Digital Outputs and Timing Out-of-Range TIMING—SINGLE PORT MODE TIMING—INTERLEAVED MODE fS/2 Spurious LAYOUT CONSIDERATIONS POWER AND GROUND RECOMMENDATIONS Exposed Paddle Thermal Heat Slug Recommendations CML RBIAS AD9601 CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE