Datasheet AD9600 (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | 10-Bit, 105 MSPS/125 MSPS/150 MSPS, 1.8 V Dual Analog-to-Digital Converter |
| 页数 / 页 | 73 / 6 — AD9600. SPECIFICATIONS DC SPECIFICATIONS. Table 1. AD9600ABCPZ-105/. … |
| 修订版 | B |
| 文件格式/大小 | PDF / 2.4 Mb |
| 文件语言 | 英语 |
AD9600. SPECIFICATIONS DC SPECIFICATIONS. Table 1. AD9600ABCPZ-105/. AD9600ABCPZ-125/. AD9600ABCPZ-150/. AD9600BCPZ-105
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AD9600 SPECIFICATIONS DC SPECIFICATIONS
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect output pins disabled, signal monitor disabled, unless otherwise noted.
Table 1. AD9600ABCPZ-105/ AD9600ABCPZ-125/ AD9600ABCPZ-150/ AD9600BCPZ-105 AD9600BCPZ-125 AD9600BCPZ-150 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION Full 10 10 10 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full ±0.3 ±0.7 ±0.3 ±0.7 ±0.3 ±0.7 % FSR Gain Error Full −3.6 −2.2 −1.0 −4.0 −2.5 −1.3 −4.3 −3.0 −1.6 % FSR Differential Nonlinearity (DNL)1 Full ±0.2 ±0.2 ±0.2 LSB 25°C ±0.1 ±0.1 ±0.1 LSB Integral Nonlinearity (INL)1 Full ±0.3 ±0.3 ±0.4 LSB 25°C ±0.1 ±0.1 ±0.1 LSB MATCHING CHARACTERISTICS Offset Error Full ±0.3 ±0.7 ±0.3 ±0.7 ±0.2 ±0.7 % FSR Gain Error Full ±0.2 ±0.8 ±0.3 ±0.8 ±0.2 ±0.8 % FSR TEMPERATURE DRIFT Offset Error Full ±15 ±15 ±15 ppm/°C Gain Error Full ±95 ±95 ±95 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Full ±5 ±16 ±5 ±16 ±5 ±16 mV Load Regulation @ 1.0 mA Full 7 7 7 mV INPUT-REFERRED NOISE VREF = 1.0 V 25°C 0.1 0.1 0.1 LSB rms ANALOG INPUT Input Span, VREF = 1.0 V Full 2 2 2 V p-p Input Capacitance2 Full 8 8 8 pF VREF INPUT RESISTANCE Full 6 6 6 kΩ POWER SUPPLIES Supply Voltage AVDD, DVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD (CMOS Mode) Full 1.7 3.3 3.6 1.7 3.3 3.6 1.7 3.3 3.6 V Supply Current I 1 AVDD Full 310 385 419 mA I 1 DVDD Full 34 42 50 mA I 1, 3 AVDD and IDVDD 365 455 495 IDRVDD (3.3 V CMOS) Full 35 36 42 mA IDRVDD (1.8 V CMOS) Full 15 18 22 mA IDRVDD (1.8 V LVDS) 42 44 46 mA POWER CONSUMPTION DC Input Full 600 650 750 800 825 890 mW Sine Wave Input1 DRVDD = 1.8 V Full 645 813 892 mW DRVDD = 3.3 V Full 740 900 990 mW Standby Power3 Full 68 77 77 mW Power-Down Power Full 2.5 6 2.5 6 2.5 6 mW 1 Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. 2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 8 for the equivalent analog input structure. 3 Standby power is measured with a dc input and the CLK+ and CLK− pins inactive )set to AVDD or AGND. Rev. B | Page 5 of 72 Document Outline FEATURES APPLICATIONS PRODUCT HIGHLIGHTS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations Single-Ended Input Configuration VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) ADC OVERRANGE AND GAIN CONTROL FAST DETECT OVERVIEW ADC FAST MAGNITUDE ADC OVERRANGE (OR) GAIN SWITCHING Coarse Upper Threshold (C_UT) Fine Upper Threshold (F_UT) Fine Lower Threshold (F_LT) Increment Gain (IG) and Decrement Gain (DG) SIGNAL MONITOR PEAK DETECTOR MODE RMS/MS MAGNITUDE MODE THRESHOLD CROSSING MODE ADDITIONAL CONTROL BITS Signal Monitor Enable Bit Complex Power Calculation Mode Enable Bit DC CORRECTION DC Correction Bandwidth DC Correction Readback DC Correction Freeze DC Correction Enable Bits SIGNAL MONITOR SPORT OUTPUT SMI SCLK SMI SDFS SMI SDO BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES CHANNEL/CHIP SYNCHRONIZATION SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP TABLE Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers MEMORY MAP MEMORY MAP REGISTER DESCRIPTION Sync Control (Register 0x100) Bit 7—Signal Monitor Sync Enable Bits [6:3]—Reserved Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Enable Fast Detect Control (Register 0x104) Bits [7:4]—Reserved Bits [3:1]—Fast Detect Mode Select Bit 0—Fast Detect Enable Coarse Upper Threshold (Register 0x105) Bits [7:3]—Reserved Bits [2:0]—Coarse Upper Threshold Fine Upper Threshold (Register 0x106 and Register 0x107) Register 0x106, Bits [7:0]—Fine Upper Threshold [7:0] Register 0x107, Bits [7:5]—Reserved Register 0x107, Bits [4:0]—Fine Upper Threshold [12:8] Fine Lower Threshold (Register 0x108 and Register 0x109) Register 0x108, Bits [7:0]—Fine Lower Threshold [7:0]Register 0x109, Bits [7:5]—ReservedRegister 0x109, Bits [4:0]—Fine Lower Threshold [12:8] Increase Gain Dwell Time (Register 0x10A andRegister 0x10B) Register 0x10A, Bits [7:0]—Increase Gain Dwell Time [7:0]Register 0x10B, Bits [7:0]—Increase Gain Dwell Time [15:8] Signal Monitor DC Correction Control (Register 0x10C) Bit 7—ReservedBit 6—DC Correction Freeze Bits [5:2]—DC Correction Bandwidth Bit 1—DC Correction for Signal Path Enable Bit 0—DC Correction for Signal Monitor Enable Signal Monitor DC Value Channel A (Register 0x10D and Register 0x10E) Register 0x10D, Bits [7:0]—DC Value Channel A [7:0] Register 0x10E, Bits [7:6]—Reserved Register 0x10E, Bits [5:0]—DC Value Channel A [13:8] Signal Monitor DC Value Channel B (Register 0x10F and Register 0x110) Register 0x10F Bits [7:0]—DC Value Channel B [7:0] Register 0x110 Bits [7:6]—Reserved Register 0x110 Bits [5:0]—DC Value Channel B [13:8] Signal Monitor SPORT Control (Register 0x111) Bit 7—Reserved Bit 6—RMS/MS Magnitude Output Enable Bit 5—Peak Detector Output Enable Bit 4—Threshold Crossing Output Enable Bits [3:2]—SPORT SMI SCLK Divide Bit 1— SPORT SMI SCLK Sleep Bit 0—Signal Monitor SPORT Output Enable Signal Monitor Control (Register 0x112) Bit 7—Complex Power Calculation Mode Enable Bits [6:4]—Reserved Bit 3—Signal Monitor RMS/MS Select Bits [2:1]—Signal Monitor Mode Bit 0—Signal Monitor Enable Signal Monitor Period (Register 0x113 to Register 0x115) Register 0x113, Bits [7:0]—Signal Monitor Period [7:0] Register 0x114, Bits [7:0]—Signal Monitor Period [15:8] Register 0x115, Bits [7:0]—Signal Monitor Period [23:16] Signal Monitor Result Channel A (Register 0x116 to Register 0x118) Register 0x116, Bits [7:0]—Signal Monitor Result Channel A [7:0] Register 0x117, Bits [7:0]—Signal Monitor Result Channel A [15:8] Register 0x118, Bits [7:4]—Reserved Register 0x118, Bits [3:0]—Signal Monitor Result Channel A [19:16] Signal Monitor Result Channel B (Register 0x119 to Register 0x11B) Register 0x119, Bits [7:0]— Signal Monitor Result Channel B [7:0] Register 0x11A, Bits [7:0]—Signal Monitor Result Channel B [15:8] Register 0x11B, Bits [7:4]—Reserved Register 0x11B, Bits [3:0]—Signal Monitor Result Channel B [19:16] APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations CML RBIAS Reference Decoupling SPI Port EVALUATION BOARD POWER SUPPLIES INPUT SIGNALS OUTPUT SIGNALS DEFAULT OPERATION AND JUMPER SELECTION SETTINGS POWER VIN RBIAS CLOCK PDWN CSB SCLK/DFS SDIO/DCS ALTERNATIVE CLOCK CONFIGURATIONS ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION SCHEMATICS EVALUATION BOARD LAYOUTS BILL OF MATERIALS OUTLINE DIMENSIONS ORDERING GUIDE
AD9600 SPECIFICATIONS DC SPECIFICATIONS
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect output pins disabled, signal monitor disabled, unless otherwise noted.
Table 1. AD9600ABCPZ-105/ AD9600ABCPZ-125/ AD9600ABCPZ-150/ AD9600BCPZ-105 AD9600BCPZ-125 AD9600BCPZ-150 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION Full 10 10 10 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full ±0.3 ±0.7 ±0.3 ±0.7 ±0.3 ±0.7 % FSR Gain Error Full −3.6 −2.2 −1.0 −4.0 −2.5 −1.3 −4.3 −3.0 −1.6 % FSR Differential Nonlinearity (DNL)1 Full ±0.2 ±0.2 ±0.2 LSB 25°C ±0.1 ±0.1 ±0.1 LSB Integral Nonlinearity (INL)1 Full ±0.3 ±0.3 ±0.4 LSB 25°C ±0.1 ±0.1 ±0.1 LSB MATCHING CHARACTERISTICS Offset Error Full ±0.3 ±0.7 ±0.3 ±0.7 ±0.2 ±0.7 % FSR Gain Error Full ±0.2 ±0.8 ±0.3 ±0.8 ±0.2 ±0.8 % FSR TEMPERATURE DRIFT Offset Error Full ±15 ±15 ±15 ppm/°C Gain Error Full ±95 ±95 ±95 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Full ±5 ±16 ±5 ±16 ±5 ±16 mV Load Regulation @ 1.0 mA Full 7 7 7 mV INPUT-REFERRED NOISE VREF = 1.0 V 25°C 0.1 0.1 0.1 LSB rms ANALOG INPUT Input Span, VREF = 1.0 V Full 2 2 2 V p-p Input Capacitance2 Full 8 8 8 pF VREF INPUT RESISTANCE Full 6 6 6 kΩ POWER SUPPLIES Supply Voltage AVDD, DVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD (CMOS Mode) Full 1.7 3.3 3.6 1.7 3.3 3.6 1.7 3.3 3.6 V Supply Current I 1 AVDD Full 310 385 419 mA I 1 DVDD Full 34 42 50 mA I 1, 3 AVDD and IDVDD 365 455 495 IDRVDD (3.3 V CMOS) Full 35 36 42 mA IDRVDD (1.8 V CMOS) Full 15 18 22 mA IDRVDD (1.8 V LVDS) 42 44 46 mA POWER CONSUMPTION DC Input Full 600 650 750 800 825 890 mW Sine Wave Input1 DRVDD = 1.8 V Full 645 813 892 mW DRVDD = 3.3 V Full 740 900 990 mW Standby Power3 Full 68 77 77 mW Power-Down Power Full 2.5 6 2.5 6 2.5 6 mW 1 Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. 2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 8 for the equivalent analog input structure. 3 Standby power is measured with a dc input and the CLK+ and CLK− pins inactive )set to AVDD or AGND. Rev. B | Page 5 of 72 Document Outline FEATURES APPLICATIONS PRODUCT HIGHLIGHTS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations Single-Ended Input Configuration VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) ADC OVERRANGE AND GAIN CONTROL FAST DETECT OVERVIEW ADC FAST MAGNITUDE ADC OVERRANGE (OR) GAIN SWITCHING Coarse Upper Threshold (C_UT) Fine Upper Threshold (F_UT) Fine Lower Threshold (F_LT) Increment Gain (IG) and Decrement Gain (DG) SIGNAL MONITOR PEAK DETECTOR MODE RMS/MS MAGNITUDE MODE THRESHOLD CROSSING MODE ADDITIONAL CONTROL BITS Signal Monitor Enable Bit Complex Power Calculation Mode Enable Bit DC CORRECTION DC Correction Bandwidth DC Correction Readback DC Correction Freeze DC Correction Enable Bits SIGNAL MONITOR SPORT OUTPUT SMI SCLK SMI SDFS SMI SDO BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES CHANNEL/CHIP SYNCHRONIZATION SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP TABLE Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers MEMORY MAP MEMORY MAP REGISTER DESCRIPTION Sync Control (Register 0x100) Bit 7—Signal Monitor Sync Enable Bits [6:3]—Reserved Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Enable Fast Detect Control (Register 0x104) Bits [7:4]—Reserved Bits [3:1]—Fast Detect Mode Select Bit 0—Fast Detect Enable Coarse Upper Threshold (Register 0x105) Bits [7:3]—Reserved Bits [2:0]—Coarse Upper Threshold Fine Upper Threshold (Register 0x106 and Register 0x107) Register 0x106, Bits [7:0]—Fine Upper Threshold [7:0] Register 0x107, Bits [7:5]—Reserved Register 0x107, Bits [4:0]—Fine Upper Threshold [12:8] Fine Lower Threshold (Register 0x108 and Register 0x109) Register 0x108, Bits [7:0]—Fine Lower Threshold [7:0]Register 0x109, Bits [7:5]—ReservedRegister 0x109, Bits [4:0]—Fine Lower Threshold [12:8] Increase Gain Dwell Time (Register 0x10A andRegister 0x10B) Register 0x10A, Bits [7:0]—Increase Gain Dwell Time [7:0]Register 0x10B, Bits [7:0]—Increase Gain Dwell Time [15:8] Signal Monitor DC Correction Control (Register 0x10C) Bit 7—ReservedBit 6—DC Correction Freeze Bits [5:2]—DC Correction Bandwidth Bit 1—DC Correction for Signal Path Enable Bit 0—DC Correction for Signal Monitor Enable Signal Monitor DC Value Channel A (Register 0x10D and Register 0x10E) Register 0x10D, Bits [7:0]—DC Value Channel A [7:0] Register 0x10E, Bits [7:6]—Reserved Register 0x10E, Bits [5:0]—DC Value Channel A [13:8] Signal Monitor DC Value Channel B (Register 0x10F and Register 0x110) Register 0x10F Bits [7:0]—DC Value Channel B [7:0] Register 0x110 Bits [7:6]—Reserved Register 0x110 Bits [5:0]—DC Value Channel B [13:8] Signal Monitor SPORT Control (Register 0x111) Bit 7—Reserved Bit 6—RMS/MS Magnitude Output Enable Bit 5—Peak Detector Output Enable Bit 4—Threshold Crossing Output Enable Bits [3:2]—SPORT SMI SCLK Divide Bit 1— SPORT SMI SCLK Sleep Bit 0—Signal Monitor SPORT Output Enable Signal Monitor Control (Register 0x112) Bit 7—Complex Power Calculation Mode Enable Bits [6:4]—Reserved Bit 3—Signal Monitor RMS/MS Select Bits [2:1]—Signal Monitor Mode Bit 0—Signal Monitor Enable Signal Monitor Period (Register 0x113 to Register 0x115) Register 0x113, Bits [7:0]—Signal Monitor Period [7:0] Register 0x114, Bits [7:0]—Signal Monitor Period [15:8] Register 0x115, Bits [7:0]—Signal Monitor Period [23:16] Signal Monitor Result Channel A (Register 0x116 to Register 0x118) Register 0x116, Bits [7:0]—Signal Monitor Result Channel A [7:0] Register 0x117, Bits [7:0]—Signal Monitor Result Channel A [15:8] Register 0x118, Bits [7:4]—Reserved Register 0x118, Bits [3:0]—Signal Monitor Result Channel A [19:16] Signal Monitor Result Channel B (Register 0x119 to Register 0x11B) Register 0x119, Bits [7:0]— Signal Monitor Result Channel B [7:0] Register 0x11A, Bits [7:0]—Signal Monitor Result Channel B [15:8] Register 0x11B, Bits [7:4]—Reserved Register 0x11B, Bits [3:0]—Signal Monitor Result Channel B [19:16] APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations CML RBIAS Reference Decoupling SPI Port EVALUATION BOARD POWER SUPPLIES INPUT SIGNALS OUTPUT SIGNALS DEFAULT OPERATION AND JUMPER SELECTION SETTINGS POWER VIN RBIAS CLOCK PDWN CSB SCLK/DFS SDIO/DCS ALTERNATIVE CLOCK CONFIGURATIONS ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION SCHEMATICS EVALUATION BOARD LAYOUTS BILL OF MATERIALS OUTLINE DIMENSIONS ORDERING GUIDE