Datasheet AD7952 (Analog Devices)

14-Bit, 1 MSPS, Differential, Programmable Input PulSAR® ADC Data Sheet AD7952 FEATURES FUNCTIONAL BLOCK DIAGRAM TEMP REFBUFIN REF REFGND VCC VEE DVDD DGND Multiple pins/software-programmable input ranges +5 V (10 V p-p), +10 V (20 V p-p), ±5 V (20 V p-p), OVDD AGND AD7952 ±10 V (40 V p-p) REF OGND AVDD AMP SERIAL DATA Pins or serial SPI®-compatible input ranges/mode selection PDREF REF PORT Throughput PDBUF SERIAL CONFIGURATION 1 MSPS (warp mode) IN+ PORT 14 SWITCHED D[13:0] CAP DAC 800 kSPS (normal mode) IN– SER/PAR 670 kSPS (impulse mode) BYTESWAP PARALLEL 14-bit resolution with no missing codes CLOCK OB/2C INTERFACE CNVST INL: ±0.3 LSB typical, ±1 LSB maximum (±61 ppm of FSR) BUSY PD CONTROL LOGIC AND RD SNR: 85 dB @ 2 kHz CALIBRATION CIRCUITRY RESET CS i CMOS® process technology
01
5 V internal reference: typical drift 3 ppm/°C; TEMP output
0 9-
WARP IMPULSE BIPOLAR TEN
658
No pipeline delay (SAR architecture)
0 Figure 1.
Parallel (14- or 8-bit bus) and serial 5 V/3.3 V interface SPI-/QSPI™-/MICROWIRE™-/DSP-compatible Table 1. 48-Lead PulSAR Selection Power dissipation 100 to 500 to 570 to 235 mW @ 1 MSPS Res 250 570 1000 >1000 Input Type (Bits) (kSPS) (kSPS) (kSPS) kSPS 10 mW @ 1 kSPS
Bipolar 14 AD7951
48-lead LQFP and 48-lead LFCSP (7 mm × 7 mm)
Differential 14 AD7952
APPLICATIONS
Bipolar
Process controls
Unipolar 16 AD7651 AD7653
Medical instruments
AD7660 AD7650 AD7667
High speed data acquisition
AD7661 AD7652
Digital signal processing
AD7664
Instrumentation
AD7666
Spectrum analysis
Bipolar 16 AD7610 AD7665 AD7612
ATE
AD7663 AD7671
GENERAL DESCRIPTION
Differential 16 AD7675 AD7676 AD7677 AD7621 Unipolar AD7622 The AD7952 is a 14-bit, charge redistribution, successive AD7623 approximation register (SAR) architecture analog-to-digital Simultaneous/ 16 AD7654 converter (ADC) fabricated on Analog Devices, Inc.’s iCMOS Multichannel AD7655 high voltage process. The device is configured through hardware or Unipolar via a dedicated write-only serial configuration port for input Differential 18 AD7678 AD7679 AD7674 AD7641 range and operating mode. The AD7952 contains a high speed Unipolar AD7643 14-bit sampling ADC, an internal conversion clock, an internal Differential 18 AD7631 AD7634 reference (and buffer), error correction circuits, and both serial Bipolar and parallel system interface ports. A falling edge on CNVST samples the fully differential analog inputs on IN+ and IN−. The AD7952 features four different analog input ranges and three different sampling modes: warp mode for the fastest throughput, normal mode for the fastest asynchronous throughput, and impulse mode where power is scaled with throughput. Operation is specified from −40°C to +85°C.
Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2007–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION OVERVIEW CONVERTER OPERATION MODES OF OPERATION Warp Mode Normal Mode Impulse Mode TRANSFER FUNCTIONS TYPICAL CONNECTION DIAGRAM ANALOG INPUTS Input Range Selection Input Structure Single-to-Differential Driver VOLTAGE REFERENCE INPUT/OUTPUT Internal Reference (REF = 5 V, PDREF = Low, PDBUF = Low) External 2.5 V Reference and Internal Buffer (REF = 5 V, PDREF = High, PDBUF = Low) External 5 V Reference (PDREF = High, PDBUF = High) Reference Decoupling Temperature Sensor POWER SUPPLIES Core Supplies High Voltage Supplies Digital Output Supply Power Sequencing Power Dissipation vs. Throughput Power Down CONVERSION CONTROL INTERFACES DIGITAL INTERFACE RESET PARALLEL INTERFACE Master Parallel Interface Slave Parallel Interface 8-Bit Interface (Master or Slave) SERIAL INTERFACE Data Interface Serial Configuration Interface MASTER SERIAL INTERFACE Internal Clock (SER/ = High, EXT/ = Low) Read During Convert (RDC = High) Read After Convert (RDC = Low, DIVSCLK[1:0] = [0 to 3]) SLAVE SERIAL INTERFACE External Clock (SER/ = High, EXT/ = High) External Discontinuous Clock Data Read After Conversion Daisy-Chain Feature External Clock Data Read During Previous Conversion External Clock Data Read After/During Conversion HARDWARE CONFIGURATION SOFTWARE CONFIGURATION MICROPROCESSOR INTERFACING SPI Interface APPLICATION INFORMATION LAYOUT GUIDELINES OUTLINE DIMENSIONS ORDERING GUIDE