Datasheet AD9222 (Analog Devices)

Octal, 12-Bit, 40/50/65 MSPS Serial LVDS 1.8 V A/D Converter Data Sheet AD9222 FEATURES FUNCTIONAL BLOCK DIAGRAM 8 ADCs integrated into 1 package AVDD PDWN DRVDD DRGND 114 mW ADC power per channel at 65 MSPS AD9222 SNR = 70 dB (to Nyquist) 12 VIN + A SERIAL D + A ENOB = 11.3 bits ADC VIN – A LVDS D – A SFDR = 80 dBc 12 VIN + B D + B SERIAL Excellent linearity: DNL = ±0.3 LSB (typical), ADC VIN – B LVDS D – B INL = ±0.4 LSB (typical) 12 VIN + C D + C SERIAL Serial LVDS (ANSI-644, default) ADC VIN – C LVDS D – C Low power, reduced signal option (similar IEEE 1596.3) 12 VIN + D SERIAL D + D Data and frame clock outputs ADC VIN – D LVDS D – D 325 MHz full-power analog bandwidth 12 VIN + E SERIAL D + E 2 V p-p input voltage range ADC VIN – E LVDS D – E 1.8 V supply operation 12 VIN + F D + F Serial port control SERIAL ADC VIN – F LVDS D – F Full-chip and individual-channel power-down modes 12 VIN + G D + G Flexible bit orientation SERIAL ADC VIN – G LVDS D – G Built-in and custom digital test pattern generation 12 Programmable clock and data alignment VIN + H SERIAL D + H ADC VIN – H LVDS D – H Programmable output resolution Standby mode VREF SENSE FCO + 0.5V FCO – APPLICATIONS DATA RATE REFT REF MULTIPLIER REFB SELECT SERIAL PORT DCO + Medical imaging and nondestructive ultrasound INTERFACE DCO – Portable ultrasound and digital beam-forming systems RBIAS AGND CSB SDIO/ SCLK/ CLK+ CLK–
001
Quadrature radio receivers ODM DTP
05967-
Diversity radio receivers
Figure 1.
Tape drives
The ADC contains several features designed to maximize
Optical networking
flexibility and minimize system cost, such as programmable
Test equipment
clock and data alignment and programmable digital test pattern
GENERAL DESCRIPTION
generation. The available digital test patterns include built-in The AD9222 is an octal, 12-bit, 40/50/65 MSPS analog-to- deterministic and pseudorandom patterns, along with custom user- digital converter (ADC) with an on-chip sample-and-hold defined test patterns entered via the serial port interface (SPI). circuit designed for low cost, low power, small size, and ease of The AD9222 is available in an RoHS compliant, 64-lead LFCSP. It is use. The product operates at a conversion rate of up to 65 MSPS specified over the industrial temperature range of −40°C to +85°C. and is optimized for outstanding dynamic performance and low
PRODUCT HIGHLIGHTS
power in applications where a smal package size is critical. 1. Small Footprint. Eight ADCs are contained in a small, The ADC requires a single 1.8 V power supply and LVPECL-/ space-saving package. CMOS-/LVDS-compatible sample rate clock for full performance 2. Low power of 114 mW/channel at 65 MSPS. operation. No external reference or driver components are 3. Ease of Use. A data clock output (DCO) is provided that required for many applications. operates at frequencies of up to 390 MHz and supports The ADC automatically multiplies the sample rate clock for double data rate (DDR) operation. the appropriate LVDS serial data rate. A data clock output (DCO) 4. User Flexibility. The SPI control offers a wide range of for capturing data on the output and a frame clock output (FCO) flexible features to meet specific system requirements. for signaling a new output byte are provided. Individual-channel 5. Pin-Compatible Family. This includes the AD9212 (10-bit) power-down is supported and typically consumes less than and AD9252 (14-bit). 2 mW when all channels are disabled.
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Document Outline Features Applications General Description Functional Block Diagram Product Highlights Table of Contents Revision History Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagrams Absolute Maximum Ratings Thermal Impedance ESD Caution Pin Configuration and Function Descriptions Equivalent Circuits Typical Performance Characteristics Theory of Operation Analog Input Considerations Differential Input Configurations Single-Ended Input Configuration Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO/ODM Pin SCLK/DTP Pin CSB Pin RBIAS Pin Voltage Reference Internal Reference Operation External Reference Operation Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations Evaluation Board Power Supplies Input Signals Output Signals Default Operation and Jumper Selection Settings Alternative Analog Input Drive Configuration Outline Dimensions Ordering Guide