Datasheet AD9461 (Analog Devices) - 9

AD9461 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS ) B S 1 1 1 1 1 1 D M D R D ND ( D D ND ND DD DD DD DD DD DD ND + – SF AG AG AV AV AV AV AV AV AG OR OR DRV DRG D15+ D15– D14+ D14– D13+ D13– D12+ D12– D11+ D11– DRV 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 DCS MODE 1 75 DRGND PIN 1 DNC 2 74 D10+ OUTPUT MODE 3 73 D10– DFS 4 72 D9+ LVDS_BIAS 5 71 D9– AVDD1 6 70 D8+ SENSE 7 69 D8– VREF 8 68 DCO+ AD9461 AGND 9 67 DCO– LVDS MODE REFT 10 66 D7+ TOP VIEW REFB 11 (Not to Scale) 65 D7– AVDD2 12 64 DRVDD AVDD2 13 63 DRGND AVDD2 14 62 D6+ AVDD2 15 61 D6– AVDD2 16 60 D5+ AVDD2 17 59 D5– AVDD1 18 58 D4+ AVDD1 19 57 D4– AVDD1 20 56 D3+ AGND 21 55 D3– VIN+ 22 54 D2+ VIN– 23 53 D2– AGND 24 52 D1+ AVDD2 25 51 D1– 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DNC = DO NOT CONNECT + – D ) ND K K ND ND N B DD2 DD2 DD2 DD2 DD2 DD2 DD1 DD1 DD1 DD2 DD1 DD2 DD1 DD1 DD1 DD1 DD S D0+ CL CL G L
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06 Figure 4. 100-Lead TQFP_EP Pin Configuration in LVDS Mode
Table 7. Pin Function Descriptions—100-Lead TQFP_EP in LVDS Mode Pin No. Mnemonic Description
1 DCS MODE Clock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible. DCS = low (AGND) to enable DCS (recommended). DCS = high (AVDD1) to disable DCS. 2 DNC Do Not Connect. This pin should float. 3 OUTPUT MODE CMOS-Compatible Output Logic Mode Control Pin. OUTPUT MODE = 0 for CMOS mode. OUTPUT MODE = 1 (AVDD1) for LVDS outputs. 4 DFS Data Format Select Pin. CMOS control pin that determines the format of the output data. DFS = high (AVDD1) for twos complement. DFS = low (ground) for offset binary format. 5 LVDS_BIAS Set Pin for LVDS Output Current. Place 3.7 kΩ resistor terminated to DRGND. 6, 18 to 20, 32 to 34, 36, AVDD1 3.3 V (±5%) Analog Supply. 38, 43 to 45, 92 to 97 7 SENSE Reference Mode Selection. Connect to AGND for internal 1.7 V reference (3.4 V p-p analog input range); connect to AVDD1 for external reference. 8 VREF 1.7 V Reference I/O. The function is dependent on the SENSE pin and external programming resistors. Decouple to ground with 0.1 μF and 10 μF capacitors. 9, 21, 24, 39, 42, 46, 91, 98, AGND Analog Ground. The exposed heat sink on the bottom of the package must be connected to 99, Exposed Heat Sink AGND. Rev. 0 | Page 8 of 28 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM APPLICATIONS GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION ANALOG INPUT AND REFERENCE OVERVIEW Internal Reference Connection Internal Reference Trim External Reference Operation Analog Inputs CLOCK INPUT CONSIDERATIONS Jitter Considerations POWER CONSIDERATIONS DIGITAL OUTPUTS LVDS Mode CMOS Mode TIMING OPERATIONAL MODE SELECTION Data Format Select Output Mode Select Duty Cycle Stabilizer SFDR Enhancement EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE