Datasheet AD7763 (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | 24-Bit, 625 kSPS, 109 dB Sigma-Delta ADC with On-Chip Buffers, Serial Interface |
| 页数 / 页 | 33 / 6 — Data Sheet. AD7763. TIMING SPECIFICATIONS. Table 3. Parameter. Limit at … |
| 修订版 | B |
| 文件格式/大小 | PDF / 652 Kb |
| 文件语言 | 英语 |
Data Sheet. AD7763. TIMING SPECIFICATIONS. Table 3. Parameter. Limit at TMIN, TMAX. Unit. Description
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Data Sheet AD7763 TIMING SPECIFICATIONS
AVDD1 = DVDD = VDRIVE = 2.5 V, AVDD2 = AVDD3 = AVDD4 = 5 V, TA = 25°C, normal mode, unless otherwise noted.
Table 3. Parameter Limit at TMIN, TMAX Unit Description
fMCLK 1 MHz min Applied master clock frequency 40 MHz max fICLK 500 kHz min Internal modulator clock derived from MCLK 20 MHz max t 1 2 1 1 × tICLK or 0.5 × tICLK typ SCO high period t 1 2 2 1 × tICLK or 0.5 × tICLK typ SCO low period t 3 3 tSCO typ DRDY low period t 4 3A 2 ns typ SCO rising edge to DRDY falling edge t 4 3B 3 ns typ SCO rising edge to DRDY rising edge t 5 3 4 32 × tSCO typ FSO low period t 4, 5 4A 1 ns typ SCO rising edge to FSO falling edge t 4, 5 4B 2 ns typ SCO falling edge to FSO rising edge t5 6.5 ns max Initial data access time t 4 6 5 ns max SCO rising edge to SDO valid t 3 7 0.5 × tSCO ns min SDO valid after SCO falling edge t 3 8 16 × tSCO typ DRDY rising edge to SDL falling edge t 3 9 tSCO typ SDL pulse width t10 5.5 ns max SDO three-state to SCO rising edge t 3 11 1 × tSCO min FSI low period t12 12 ns min SDI setup time t13 10 ns min SDI hold time t14 12 ns min FSI setup time t 3 15 16 × tSCO typ SDL falling edge to SDL falling edge 1 tICLK = 1/fICLK. 2 SCO frequency selected by SCR and CDIV pins. 3 tSCO = t1 + t2. 4 All edges mentioned refer to SCP = 0. Invert SCO edges for SCP = 1. 5 In decimate × 32 mode, this time specification applies only when CDIV = 0 and SCR =1. For all other combinations of CDIV and SCR in decimate × 32 mode, the FSO signal is constantly logic low. Rev. B | Page 5 of 32 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Terminology Typical Performance Characteristics Theory of Operation AD7763 Interface Reading Data Using the SPI Interface Synchronization Sharing the Serial Bus Writing to the AD7763 Reading Status and Other Registers Reading Data Using the I2S Interface Clocking the AD7763 Example 1 Example 2 Driving the AD7763 Using the AD7763 Bias Resistor Selection Decoupling and Layout Recommendations Supply Decoupling Additional Decoupling Reference Voltage Filtering Differential Amplifier Components Exposed Paddle Layout Considerations Programmable FIR Filter Downloading a User-Defined Filter Example Filter Download Registers Control Register 1—Address 0x001 Default Value 0x001A Control Register 2—Address 0x002 Default Value 0x009B Status Register (Read Only) Offset Register—Address 0x003 Non Bit-Mapped, Default Value 0x0000 Gain Register—Address 0x004 Non Bit-Mapped, Default Value 0xA000 Overrange Register—Address 0x005 Non Bit-Mapped, Default Value 0xCCCC Outline Dimensions Ordering Guide
Data Sheet AD7763 TIMING SPECIFICATIONS
AVDD1 = DVDD = VDRIVE = 2.5 V, AVDD2 = AVDD3 = AVDD4 = 5 V, TA = 25°C, normal mode, unless otherwise noted.
Table 3. Parameter Limit at TMIN, TMAX Unit Description
fMCLK 1 MHz min Applied master clock frequency 40 MHz max fICLK 500 kHz min Internal modulator clock derived from MCLK 20 MHz max t 1 2 1 1 × tICLK or 0.5 × tICLK typ SCO high period t 1 2 2 1 × tICLK or 0.5 × tICLK typ SCO low period t 3 3 tSCO typ DRDY low period t 4 3A 2 ns typ SCO rising edge to DRDY falling edge t 4 3B 3 ns typ SCO rising edge to DRDY rising edge t 5 3 4 32 × tSCO typ FSO low period t 4, 5 4A 1 ns typ SCO rising edge to FSO falling edge t 4, 5 4B 2 ns typ SCO falling edge to FSO rising edge t5 6.5 ns max Initial data access time t 4 6 5 ns max SCO rising edge to SDO valid t 3 7 0.5 × tSCO ns min SDO valid after SCO falling edge t 3 8 16 × tSCO typ DRDY rising edge to SDL falling edge t 3 9 tSCO typ SDL pulse width t10 5.5 ns max SDO three-state to SCO rising edge t 3 11 1 × tSCO min FSI low period t12 12 ns min SDI setup time t13 10 ns min SDI hold time t14 12 ns min FSI setup time t 3 15 16 × tSCO typ SDL falling edge to SDL falling edge 1 tICLK = 1/fICLK. 2 SCO frequency selected by SCR and CDIV pins. 3 tSCO = t1 + t2. 4 All edges mentioned refer to SCP = 0. Invert SCO edges for SCP = 1. 5 In decimate × 32 mode, this time specification applies only when CDIV = 0 and SCR =1. For all other combinations of CDIV and SCR in decimate × 32 mode, the FSO signal is constantly logic low. Rev. B | Page 5 of 32 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Terminology Typical Performance Characteristics Theory of Operation AD7763 Interface Reading Data Using the SPI Interface Synchronization Sharing the Serial Bus Writing to the AD7763 Reading Status and Other Registers Reading Data Using the I2S Interface Clocking the AD7763 Example 1 Example 2 Driving the AD7763 Using the AD7763 Bias Resistor Selection Decoupling and Layout Recommendations Supply Decoupling Additional Decoupling Reference Voltage Filtering Differential Amplifier Components Exposed Paddle Layout Considerations Programmable FIR Filter Downloading a User-Defined Filter Example Filter Download Registers Control Register 1—Address 0x001 Default Value 0x001A Control Register 2—Address 0x002 Default Value 0x009B Status Register (Read Only) Offset Register—Address 0x003 Non Bit-Mapped, Default Value 0x0000 Gain Register—Address 0x004 Non Bit-Mapped, Default Value 0xA000 Overrange Register—Address 0x005 Non Bit-Mapped, Default Value 0xCCCC Outline Dimensions Ordering Guide