Datasheet AD7276, AD7277, AD7278 (Analog Devices) - 7
| 制造商 | Analog Devices |
| 描述 | 3 MSPS, 8-Bit ADC in 8-Lead MSOP and 6-Lead TSOT |
| 页数 / 页 | 28 / 7 — Data Sheet. AD7276/AD7277/AD7278. AD7278. SPECIFICATIONS. Table 4. … |
| 修订版 | D |
| 文件格式/大小 | PDF / 596 Kb |
| 文件语言 | 英语 |
Data Sheet. AD7276/AD7277/AD7278. AD7278. SPECIFICATIONS. Table 4. Parameter. A Grade1, 2. B Grad. e1, 2. Unit. Test Conditions/Comments
该数据表的模型线
- AD7276ARMZ AD7276ARMZ-REEL AD7276AUJZ-500RL7 AD7276AUJZ-REEL7 AD7276BRMZ AD7276BRMZ-REEL AD7276BUJZ-500RL7 AD7276BUJZ-REEL7 AD7276YUJZ-500RL7 AD7276YUJZ-REEL7
文件文字版本
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Data Sheet AD7276/AD7277/AD7278 AD7278 SPECIFICATIONS
VDD = 2.35 V to 3.6 V, fSCLK = 48 MHz, fSAMPLE = 3 MSPS, TA = TMIN to TMAX, unless otherwise noted.
Table 4. Parameter A Grade1, 2 B Grad e1, 2 Unit Test Conditions/Comments
DYNAMIC PERFORMANCE f = 1 MHz sine wave IN Signal-to-Noise + Distortion (SINAD)3 49 49 dB min Total Harmonic Distortion (THD)3 −66 −67 dB max −73 −73 dB typ Peak Harmonic or Spurious Noise (SFDR)3 −69 −69 dB typ Intermodulation Distortion (IMD)3 Second-Order Terms −76 −76 dB typ fa = 1 MHz, fb = 0.97 MHz Third-Order Terms −76 −76 dB typ fa = 1 MHz, fb = 0.97 MHz Aperture Delay 5 5 ns typ Aperture Jitter 18 18 ps typ Full Power Bandwidth 74 74 MHz typ @ 3 dB Full Power Bandwidth 10 10 MHz typ @ 0.1 dB DC ACCURACY Resolution 8 8 Bits Integral Nonlinearity3 ±0.2 ±0.2 LSB max Differential Nonlinearity3 ±0.3 ±0.3 LSB max Guaranteed no missed codes to 8 bits Offset Error3 ±0.9 ±0.5 LSB max Gain Error3 ±1.2 ±1 LSB max Total Unadjusted Error (TUE)3 ±1.5 ±1.5 LSB max ANALOG INPUT Input Voltage Ranges 0 to V 0 to V V DD DD DC Leakage Current ±1 ±1 µA max −40°C to +85°C ±5.5 ±5.5 µA max 85°C to 125°C Input Capacitance 42 42 pF typ When in track 10 10 pF typ When in hold LOGIC INPUTS Input High Voltage, V 1.7 1.7 V min 2.35 V ≤ V ≤ 2.7 V INH DD 2 2 V min 2.7 V < V ≤ 3.6 V DD Input Low Voltage, V 0.7 0.7 V max 2.35 V ≤ V ≤ 2.7 V INL DD 0.8 0.8 V max 2.7 V < V ≤ 3.6 V DD Input Current, I ±1 ±1 µA max IN Input Capacitance, C 4 2 2 pF typ IN LOGIC OUTPUTS Output High Voltage, V V − 0.2 V − 0.2 V min I = 200 µA, V = 2.35 V to 3.6 V OH DD DD SOURCE DD Output Low Voltage, V 0.2 0.2 V max I = 200 µA OL SINK Floating-State Leakage Current ±2.5 ±2.5 µA max Floating-State Output Capacitance4 4.5 4.5 pF typ Output Coding Straight (natural) binary CONVERSION RATE Conversion Time 208 208 ns max 10 SCLK cycles with SCLK at 48 MHz Track-and-Hold Acquisition Time3 60 60 ns min Throughput Rate 4 4 MSPS max SCLK at 48 MHz Rev. D | Page 7 of 28 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AD7276 SPECIFICATIONS AD7277 SPECIFICATIONS AD7278 SPECIFICATIONS TIMING SPECIFICATIONS—AD7276/AD7277/AD7278 TIMING EXAMPLES Timing Example 1 Timing Example 2 ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM Analog Input Digital Inputs MODES OF OPERATION Normal Mode Partial Power-Down Mode Full Power-Down Mode Power-Up Times POWER VS. THROUGHPUT RATE SERIAL INTERFACE AD7278 IN A 10 SCLK CYCLE SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7276/AD7277/AD7278 to Blackfin Processor APPLICATION HINTS GROUNDING AND LAYOUT EVALUATING PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE NOTES
Data Sheet AD7276/AD7277/AD7278 AD7278 SPECIFICATIONS
VDD = 2.35 V to 3.6 V, fSCLK = 48 MHz, fSAMPLE = 3 MSPS, TA = TMIN to TMAX, unless otherwise noted.
Table 4. Parameter A Grade1, 2 B Grad e1, 2 Unit Test Conditions/Comments
DYNAMIC PERFORMANCE f = 1 MHz sine wave IN Signal-to-Noise + Distortion (SINAD)3 49 49 dB min Total Harmonic Distortion (THD)3 −66 −67 dB max −73 −73 dB typ Peak Harmonic or Spurious Noise (SFDR)3 −69 −69 dB typ Intermodulation Distortion (IMD)3 Second-Order Terms −76 −76 dB typ fa = 1 MHz, fb = 0.97 MHz Third-Order Terms −76 −76 dB typ fa = 1 MHz, fb = 0.97 MHz Aperture Delay 5 5 ns typ Aperture Jitter 18 18 ps typ Full Power Bandwidth 74 74 MHz typ @ 3 dB Full Power Bandwidth 10 10 MHz typ @ 0.1 dB DC ACCURACY Resolution 8 8 Bits Integral Nonlinearity3 ±0.2 ±0.2 LSB max Differential Nonlinearity3 ±0.3 ±0.3 LSB max Guaranteed no missed codes to 8 bits Offset Error3 ±0.9 ±0.5 LSB max Gain Error3 ±1.2 ±1 LSB max Total Unadjusted Error (TUE)3 ±1.5 ±1.5 LSB max ANALOG INPUT Input Voltage Ranges 0 to V 0 to V V DD DD DC Leakage Current ±1 ±1 µA max −40°C to +85°C ±5.5 ±5.5 µA max 85°C to 125°C Input Capacitance 42 42 pF typ When in track 10 10 pF typ When in hold LOGIC INPUTS Input High Voltage, V 1.7 1.7 V min 2.35 V ≤ V ≤ 2.7 V INH DD 2 2 V min 2.7 V < V ≤ 3.6 V DD Input Low Voltage, V 0.7 0.7 V max 2.35 V ≤ V ≤ 2.7 V INL DD 0.8 0.8 V max 2.7 V < V ≤ 3.6 V DD Input Current, I ±1 ±1 µA max IN Input Capacitance, C 4 2 2 pF typ IN LOGIC OUTPUTS Output High Voltage, V V − 0.2 V − 0.2 V min I = 200 µA, V = 2.35 V to 3.6 V OH DD DD SOURCE DD Output Low Voltage, V 0.2 0.2 V max I = 200 µA OL SINK Floating-State Leakage Current ±2.5 ±2.5 µA max Floating-State Output Capacitance4 4.5 4.5 pF typ Output Coding Straight (natural) binary CONVERSION RATE Conversion Time 208 208 ns max 10 SCLK cycles with SCLK at 48 MHz Track-and-Hold Acquisition Time3 60 60 ns min Throughput Rate 4 4 MSPS max SCLK at 48 MHz Rev. D | Page 7 of 28 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AD7276 SPECIFICATIONS AD7277 SPECIFICATIONS AD7278 SPECIFICATIONS TIMING SPECIFICATIONS—AD7276/AD7277/AD7278 TIMING EXAMPLES Timing Example 1 Timing Example 2 ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM Analog Input Digital Inputs MODES OF OPERATION Normal Mode Partial Power-Down Mode Full Power-Down Mode Power-Up Times POWER VS. THROUGHPUT RATE SERIAL INTERFACE AD7278 IN A 10 SCLK CYCLE SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7276/AD7277/AD7278 to Blackfin Processor APPLICATION HINTS GROUNDING AND LAYOUT EVALUATING PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE NOTES