Datasheet AD7441, AD7451 (Analog Devices) - 7

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AD7441/AD7451 TIMING SPECIFICATIONS1
VDD = 2.7 V to 5.25 V; fSCLK = 18 MHz; fS = 1 MSPS; VREF = 2.5 V; TA = TMIN to TMAX, unless otherwise noted.
Table 3. Parameter Limit at TMIN, TMAX Unit Description
f 2 SCLK 10 kHz min 18 MHz max tCONVERT 16 × tSCLK tSCLK = 1/fSCLK 888 ns max tQUIET 60 ns min Minimum quiet time between end of a serial read and next falling edge of CS t1 10 ns min Minimum CS pulse width t2 10 ns min CS falling edge to SCLK falling edge setup time t 3 3 20 ns max Delay from CS falling edge until SDATA three-state disabled t4 40 ns max Data access time after SCLK falling edge t5 0.4 tSCLK ns min SCLK high pulse width t6 0.4 tSCLK ns min SCLK low pulse width t7 10 ns min SCLK edge to data valid hold time t 4 8 10 ns min SCLK falling edge to SDATA, three-state enabled 35 ns max SCLK falling edge to SDATA, three-state enabled t 5 POWER-UP 1 μs max Power-up time from full power-down 1 Guaranteed by characterization. All input signals are specified with tRISE = tFALL = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. See Figure 2, Figure 3, and the Serial Interface section. 2 Mark/space ratio for the SCLK input is 40/60 to 60/40. 3 Measured with the load circuit of Figure 4 and defined as the time required for the output to cross 0.8 V or 2.4 V with VDD = 5 V and the time required for an output to cross 0.4 V or 2.0 V for VDD = 3 V. 4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 4. The measured number is then extrapolated back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time (t8) quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 5 See the Power-Up Time section.
TIMING DIAGRAMS t1 CS t t CONVERT 2 t5 B SCLK 1 2 3 4 5 13 14 15 16 t t 6 t8 3 t t7 4 tQUIET
02
SDATA 0 0 0 0 DB11 DB10 DB2 DB1 DB0
0 3-
4 LEADING ZEROS THREE-STATE
15 03 Figure 2. AD7451 Serial Interface Timing Diagram
t1 CS t t CONVERT 2 t5 B SCLK 1 2 3 4 5 13 14 15 16 t t 6 t8 3 t t7 4 tQUIET
03
SDATA 0 0 0 0 DB9 DB8 DB0 0 0
0 3-
4 LEADING ZEROS 2 TRAILING ZEROS THREE-STATE
15 03 Figure 3. AD7441 Serial Interface Timing Diagram Rev. D | Page 7 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT ANALOG INPUT STRUCTURE DIGITAL INPUTS REFERENCE SERIAL INTERFACE Timing Example 1 Timing Example 2 MODES OF OPERATION NORMAL MODE POWER-DOWN MODE Power-Up Time POWER VS. THROUGHPUT RATE MICROPROCESSOR AND DSP INTERFACING AD7441/AD7451 to ADSP-21xx AD7441/AD7451 to TMS320C5x/C54x AD7441/AD7451 to DSP56xxx GROUNDING AND LAYOUT HINTS EVALUATING PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE