Datasheet AD7440, AD7450A (Analog Devices) - 7

link to page 7 link to page 7 link to page 8 link to page 8
Data Sheet AD7440/AD7450A TIMING SPECIFICATIONS
Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. See Figure 2, Figure 3, and the Serial Interface section.
Table 3. VDD = 2.7 V to 3.6 V, fSCLK = 18 MHz, fS = 1 MSPS, VREF = 2.0 V; VDD = 4.75 V to 5.25 V, fSCLK = 18 MHz, fS = 1 MSPS, V 1 REF = 2.5 V; VCM = VREF; TA = TMIN to TMAX, unless otherwise noted. Parameter Limit at TMIN, TMAX Unit Description
f 2 SCLK 10 kHz min 18 MHz max tCONVERT 16 × tSCLK tSCLK = 1/fSCLK 888 ns max tQUIET 60 ns min Minimum quiet time between the end of a serial read and the next falling edge of CS t1 10 ns min Minimum CS pulse width t2 10 ns min CS falling edge to SCLK falling edge setup time t 3 3 20 ns max Delay from CS falling edge until SDATA three-state disabled t 3 4 40 ns max Data access time after SCLK falling edge t5 0.4 tSCLK ns min SCLK high pulse width t6 0.4 tSCLK ns min SCLK low pulse width t7 10 ns min SCLK edge to data valid hold time t 4 8 10 ns min SCLK falling edge to SDATA three-state enabled 35 ns max SCLK falling edge to SDATA three-state enabled t 5 POWER-UP 1 μs max Power-up time from full power-down 1 Common-mode voltage. 2 Mark/space ratio for the SCLK input is 40/60 to 60/40. 3 Measured with the load circuit of Figure 4 and defined as the time required for the output to cross 0.8 V or 2.4 V with VDD = 5 V or 0.4 V or 2.0 V for VDD = 3 V. 4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 4. The measured number is then extrapolated back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t8, quoted in the Timing Specifications is the true bus relinquish time of the part and is independent of the bus loading. 5 See Power-Up Time section.
t1 CS t t CONVERT 2 t5 B SCLK 1 2 3 4 5 13 14 15 16 t t 6 t8 3 t t7
-002
4
A
tQUIET
051-
SDATA 0 0 0 0 DB11 DB10 DB2 DB1 DB0
03
4 LEADING ZEROS THREE-STATE
Figure 2. AD7450A Serial Interface Timing Diagram
t1 CS t t CONVERT 2 t5 B SCLK 1 2 3 4 5 13 14 15 16 t t 6 t8 3 t t7
-003
4
A
tQUIET
3051-
SDATA 0 0 0 0 DB9 DB8 DB0 0 0
0
4 LEADING ZEROS 2 TRAILING ZEROS THREE-STATE
Figure 3. AD7440 Serial Interface Timing Diagram Rev. D | Page 7 of 27 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY AD7440–SPECIFICATIONS AD7450A–SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TERMINOLOGY AD7440/AD7450A–TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT Analog Input Structure DRIVING DIFFERENTIAL INPUTS Differential Amplifier Op Amp Pair RF Transformer DIGITAL INPUTS REFERENCE Example 1 Example 2 SINGLE-ENDED OPERATION SERIAL INTERFACE Timing Example 1 Timing Example 2 MODES OF OPERATION NORMAL MODE POWER-DOWN MODE POWER-UP TIME POWER vs. THROUGHPUT RATE GROUNDING AND LAYOUT HINTS EVALUATING THE AD7440/AD7450A PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE