Datasheet AD7782 (Analog Devices) - 5
| 制造商 | Analog Devices |
| 描述 | 2-Channel, Read-Only, Pin-Configured, 24-bit Sigma-Delta ADC |
| 页数 / 页 | 13 / 5 — AD7782 |
| 修订版 | A |
| 文件格式/大小 | PDF / 648 Kb |
| 文件语言 | 英语 |
AD7782
该数据表的模型线
文件文字版本
AD7782 TIMING CHARACTERISTICS1, 2 (VDD = 2.7 V to 3.6 V or VDD = 4.75 V to 5.25 V; GND = 0 V; XTAL = 32.768 kHz; Input Logic 0 = 0 V, Logic 1 = VDD unless otherwise noted.) Limit at TMIN, TMAX Parameter (B Version) Unit Conditions/Comments
t1 30.5176 µs typ Crystal Oscillator Period tADC 50.54 ms typ 19.79 Hz Update Rate t2 0 ns min CH1/CH2 Select to CS Setup Time t3 0 ns min CS Falling Edge to DOUT Active 60 ns max VDD = 4.75 V to 5.25 V 80 ns max VDD = 2.7 V to 3.6 V t4 2 × t ADC ns typ Channel Settling Time t 3 5 0 ns min SCLK Active Edge to Data Valid Delay4 60 ns max VDD = 4.75 V to 5.25 V 80 ns max VDD = 2.7 V to 3.6 V t 5 8 10 ns min Bus Relinquish Time after CS Inactive Edge 80 ns max t9 0 ns min CS Rising Edge to SCLK Inactive Edge Hold Time t10 10 ns min SCLK Inactive to DOUT High 80 ns max Slave Mode Timing t6 100 ns min SCLK High Pulsewidth t7 100 ns min SCLK Low Pulsewidth Master Mode Timing t6 t1/2 µs typ SCLK High Pulsewidth t7 t1/2 µs typ SCLK Low Pulsewidth t11 t1/2 µs min DOUT Low to First SCLK Active Edge4 3t1/2 µs max NOTES 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. 2 See Figure 2. 3 These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the VOL or VOH limits. 4 SCLK active edge is falling edge of SCLK. 5These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances.
ISINK (1.6mA WITH VDD = 5V 100
A WITH VDD = 3V) TO OUTPUT 1.6V PIN 50pF ISOURCE ( 200
A WITH VDD = 5V 100
A WITH VDD = 3V)
Figure 1. Load Circuit for Timing Characterization –4– REV. A
t1 30.5176 µs typ Crystal Oscillator Period tADC 50.54 ms typ 19.79 Hz Update Rate t2 0 ns min CH1/CH2 Select to CS Setup Time t3 0 ns min CS Falling Edge to DOUT Active 60 ns max VDD = 4.75 V to 5.25 V 80 ns max VDD = 2.7 V to 3.6 V t4 2 × t ADC ns typ Channel Settling Time t 3 5 0 ns min SCLK Active Edge to Data Valid Delay4 60 ns max VDD = 4.75 V to 5.25 V 80 ns max VDD = 2.7 V to 3.6 V t 5 8 10 ns min Bus Relinquish Time after CS Inactive Edge 80 ns max t9 0 ns min CS Rising Edge to SCLK Inactive Edge Hold Time t10 10 ns min SCLK Inactive to DOUT High 80 ns max Slave Mode Timing t6 100 ns min SCLK High Pulsewidth t7 100 ns min SCLK Low Pulsewidth Master Mode Timing t6 t1/2 µs typ SCLK High Pulsewidth t7 t1/2 µs typ SCLK Low Pulsewidth t11 t1/2 µs min DOUT Low to First SCLK Active Edge4 3t1/2 µs max NOTES 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. 2 See Figure 2. 3 These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the VOL or VOH limits. 4 SCLK active edge is falling edge of SCLK. 5These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances.
ISINK (1.6mA WITH VDD = 5V 100
A WITH VDD = 3V) TO OUTPUT 1.6V PIN 50pF ISOURCE ( 200
A WITH VDD = 5V 100
A WITH VDD = 3V)
Figure 1. Load Circuit for Timing Characterization –4– REV. A