Datasheet AD7730, AD7730L (Analog Devices)
| 制造商 | Analog Devices |
| 描述 | CMOS, 24-Bit Low Power Sigma-Delta ADC for Bridge Transducer Applications |
| 页数 / 页 | 53 / 1 — Bridge Transducer ADC. AD7730/AD7730L. KEY FEATURES. Resolution of … |
| 修订版 | B |
| 文件格式/大小 | PDF / 323 Kb |
| 文件语言 | 英语 |
Bridge Transducer ADC. AD7730/AD7730L. KEY FEATURES. Resolution of 230,000 Counts (Peak-to-Peak). Offset Drift: 5 nV/
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a
Bridge Transducer ADC AD7730/AD7730L
The modulator output is processed by a low pass programmable
KEY FEATURES
digital filter, allowing adjustment of filter cutoff, output rate and
Resolution of 230,000 Counts (Peak-to-Peak)
settling time.
Offset Drift: 5 nV/ C Gain Drift: 2 ppm/ C
The part features two buffered differential programmable gain
Line Frequency Rejection: >150 dB
analog inputs as well as a differential reference input. The part
Buffered Differential Inputs
operates from a single +5 V supply. It accepts four unipolar
Programmable Filter Cutoffs
analog input ranges: 0 mV to +10 mV, +20 mV, +40 mV and
Specified for Drift Over Time
+80 mV and four bipolar ranges: ±10 mV, ± 20 mV, ± 40 mV
Operates with Reference Voltages of 1 V to 5 V
and ± 80 mV. The peak-to-peak resolution achievable directly from the part is 1 in 230,000 counts. An on-chip 6-bit DAC
ADDITIONAL FEATURES
allows the removal of TARE voltages. Clock signals for synchro-
Two-Channel Programmable Gain Front End
nizing ac excitation of the bridge are also provided.
On-Chip DAC for Offset/TARE Removal FASTStep™ Mode
The serial interface on the part can be configured for three-wire
AC or DC Excitation
operation and is compatible with microcontrollers and digital
Single Supply Operation
signal processors. The AD7730 contains self-calibration and system calibration options, and features an offset drift of less
APPLICATIONS
than 5 nV/°C and a gain drift of less than 2 ppm/°C.
Weigh Scales
The AD7730 is available in a 24-pin plastic DIP, a 24-lead
Pressure Measurement
SOIC and 24-lead TSSOP package. The AD7730L is available in a 24-lead SOIC and 24-lead TSSOP package.
GENERAL DESCRIPTION
The AD7730 is a complete analog front end for weigh-scale and
NOTE
pressure measurement applications. The device accepts low- The description of the functions and operation given in this data level signals directly from a transducer and outputs a serial sheet apply to both the AD7730 and AD7730L. Specifications digital word. The input signal is applied to a proprietary pro- and performance parameters differ for the parts. Specifications grammable gain front end based around an analog modulator. for the AD7730L are outlined in Appendix A.
FUNCTIONAL BLOCK DIAGRAM AVDD DVDD REF IN(–) REF IN(+) REFERENCE DETECT AD7730 VBIAS AVDD AIN1(+) STANDBY SIGMA-DELTA A/D CONVERTER 100nA BUFFER AIN1(–) SIGMA- PROGRAMMABLE SYNC DELTA DIGITAL + MUX PGA MODULATOR FILTER +/– AIN2(+)/D1 100nA MCLK IN 6-BIT CLOCK AIN2(–)/D0 AGND DAC SERIAL INTERFACE GENERATION MCLK OUT AND CONTROL LOGIC REGISTER BANK SCLK CS CALIBRATION MICROCONTROLLER DIN ACX AC DOUT EXCITATION ACX CLOCK AGND DGND POL RDY RESET
FASTStep is a trademark of Analog Devices, Inc. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
which may result from its use. No license is granted by implication or
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
otherwise under any patent or patent rights of Analog Devices.
Fax: 781/461-3113 © Analog Devices, Inc., 2012
Bridge Transducer ADC AD7730/AD7730L
The modulator output is processed by a low pass programmable
KEY FEATURES
digital filter, allowing adjustment of filter cutoff, output rate and
Resolution of 230,000 Counts (Peak-to-Peak)
settling time.
Offset Drift: 5 nV/ C Gain Drift: 2 ppm/ C
The part features two buffered differential programmable gain
Line Frequency Rejection: >150 dB
analog inputs as well as a differential reference input. The part
Buffered Differential Inputs
operates from a single +5 V supply. It accepts four unipolar
Programmable Filter Cutoffs
analog input ranges: 0 mV to +10 mV, +20 mV, +40 mV and
Specified for Drift Over Time
+80 mV and four bipolar ranges: ±10 mV, ± 20 mV, ± 40 mV
Operates with Reference Voltages of 1 V to 5 V
and ± 80 mV. The peak-to-peak resolution achievable directly from the part is 1 in 230,000 counts. An on-chip 6-bit DAC
ADDITIONAL FEATURES
allows the removal of TARE voltages. Clock signals for synchro-
Two-Channel Programmable Gain Front End
nizing ac excitation of the bridge are also provided.
On-Chip DAC for Offset/TARE Removal FASTStep™ Mode
The serial interface on the part can be configured for three-wire
AC or DC Excitation
operation and is compatible with microcontrollers and digital
Single Supply Operation
signal processors. The AD7730 contains self-calibration and system calibration options, and features an offset drift of less
APPLICATIONS
than 5 nV/°C and a gain drift of less than 2 ppm/°C.
Weigh Scales
The AD7730 is available in a 24-pin plastic DIP, a 24-lead
Pressure Measurement
SOIC and 24-lead TSSOP package. The AD7730L is available in a 24-lead SOIC and 24-lead TSSOP package.
GENERAL DESCRIPTION
The AD7730 is a complete analog front end for weigh-scale and
NOTE
pressure measurement applications. The device accepts low- The description of the functions and operation given in this data level signals directly from a transducer and outputs a serial sheet apply to both the AD7730 and AD7730L. Specifications digital word. The input signal is applied to a proprietary pro- and performance parameters differ for the parts. Specifications grammable gain front end based around an analog modulator. for the AD7730L are outlined in Appendix A.
FUNCTIONAL BLOCK DIAGRAM AVDD DVDD REF IN(–) REF IN(+) REFERENCE DETECT AD7730 VBIAS AVDD AIN1(+) STANDBY SIGMA-DELTA A/D CONVERTER 100nA BUFFER AIN1(–) SIGMA- PROGRAMMABLE SYNC DELTA DIGITAL + MUX PGA MODULATOR FILTER +/– AIN2(+)/D1 100nA MCLK IN 6-BIT CLOCK AIN2(–)/D0 AGND DAC SERIAL INTERFACE GENERATION MCLK OUT AND CONTROL LOGIC REGISTER BANK SCLK CS CALIBRATION MICROCONTROLLER DIN ACX AC DOUT EXCITATION ACX CLOCK AGND DGND POL RDY RESET
FASTStep is a trademark of Analog Devices, Inc. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
which may result from its use. No license is granted by implication or
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
otherwise under any patent or patent rights of Analog Devices.
Fax: 781/461-3113 © Analog Devices, Inc., 2012