Datasheet AD7730, AD7730L (Analog Devices) - 4

AD7730/AD7730L
NOTES 11Temperature range: –40°C to +85°C. 12Sample tested during initial release. 13The offset (or zero) numbers with CHP = 1 are typically 3 μV precalibration. Internal zero-scale calibration reduces this by about 1 μV. Offset numbers with CHP = 0 can be up to 1 mV precalibration. Internal zero-scale calibration reduces this to 2 μV typical. System zero-scale calibration reduces offset numbers with CHP = 1 and CHP = 0 to the order of the noise. Gain errors can be up to 3000 ppm precalibration with CHP = 0 and CHP = 1. Performing internal full-scale calibrations on the 80 mV range reduces the gain error to less than 100 ppm for the 80 mV and 40 mV ranges, to about 250 ppm for the 20 mV range and to about 500 ppm on the 10 mV range. System full-scale calibration reduces this to the order of the noise. Positive and negative full-scale errors can be calculated from the offset and gain errors. 14These numbers are generated during life testing of the part. 15Positive Full-Scale Error includes Offset Errors (Unipolar Offset Error or Bipolar Zero Error) and applies to both unipolar and bipolar input ranges. See Terminology. 16Recalibration at any temperature will remove these errors. 17Full-Scale Drift includes Offset Drift (Unipolar Offset Drift or Bipolar Zero Drift) and applies to both unipolar and bipolar input ranges. 18Gain Error is a measure of the difference between the measured and the ideal span between any two points in the transfer function. The two points used to calculate the gain error are positive full scale and negative full scale. See Terminology. 19Gain Error Drift is a span drift and is effectively the drift of the part if zero-scale calibrations only were performed. 10No Missing Codes performance with CHP = 0 and SKIP = 1 is reduced below 24 bits for SF words lower than 180 decimal. 11The analog input voltage range on the AIN1(+) and AIN2(+) inputs is given here with respect to the voltage on the AIN1(–) and AIN2(–) inputs respectively. 12The common-mode voltage range on the input pairs applies provided the absolute input voltage specification is obeyed. 13The common-mode voltage range on the reference input pair (REF IN(+) and REF IN(–)) applies provided the absolute input voltage specification is obeyed. 14These logic output levels apply to the MCLK OUT output only when it is loaded with a single CMOS load. 15VDD refers to DVDD for all logic outputs expect D0, D1, ACX and ACX where it refers to AVDD. In other words, the output logic high for these four outputs is determined by AVDD. 16This number represents the total drift of the channel with a zero input and the DAC output near full scale. 17After calibration, if the input voltage exceeds positive full scale, the converter will output all 1s. If the input is less than negative full scale, the device outputs all 0s. 18These calibration and span limits apply provided the absolute input voltage specification is obeyed. The offset calibration limit applies to both the unipolar zero point and the bipolar zero point. Specifications subject to change without notice.
(AV TIMING CHARACTERISTICS1, 2 DD = +4.75 V to +5.25 V; DVDD = +2.7 V to +5.25 V; AGND = DGND = 0 V; fCLK IN = 4.9152 MHz; Input Logic 0 = 0 V, Logic 1 = DVDD unless otherwise noted). Limit at TMIN to TMAX Parameter (B Version) Units Conditions/Comments
Master Clock Range 1 MHz min For Specified Performance 5 MHz max t1 50 ns min SYNC Pulsewidth t2 50 ns min RESET Pulsewidth
Read Operation
t3 0 ns min RDY to CS Setup Time t4 0 ns min CS Falling Edge to SCLK Active Edge Setup Time3 t 4 5 0 ns min SCLK Active Edge to Data Valid Delay3 60 ns max DVDD = +4.75 V to +5.25 V 80 ns max DVDD = +2.75 V to +3.3 V t 4, 5 5A 0 ns min CS Falling Edge to Data Valid Delay 60 ns max DVDD = +4.75 V to +5.25 V 80 ns max DVDD = +2.7 V to +3.3 V t6 100 ns min SCLK High Pulsewidth t7 100 ns min SCLK Low Pulsewidth t8 0 ns min CS Rising Edge to SCLK Inactive Edge Hold Time3 t 6 9 10 ns min Bus Relinquish Time after SCLK Inactive Edge3 80 ns max t10 100 ns max SCLK Active Edge to RDY High3, 7
Write Operation
t11 0 ns min CS Falling Edge to SCLK Active Edge Setup Time3 t12 30 ns min Data Valid to SCLK Edge Setup Time t13 25 ns min Data Valid to SCLK Edge Hold Time t14 100 ns min SCLK High Pulsewidth t15 100 ns min SCLK Low Pulsewidth t16 0 ns min CS Rising Edge to SCLK Edge Hold Time NOTES 1Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DV DD) and timed from a voltage level of 1.6 V. 2See Figures 18 and 19. 3SCLK active edge is falling edge of SCLK with POL = 1; SCLK active edge is rising edge of SCLK with POL = 0. 4These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the VOL or VOH limits. 5This specification only comes into play if CS goes low while SCLK is low (POL = 1) or if CS goes low while SCLK is high (POL = 0). It is primarily required for interfacing to DSP machines. 6These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. 7RDY returns high after the first read from the device after an output update. The same data can be read again, if required, while RDY is high, although care should be taken that subsequent reads do not occur close to the next output update. –4– REV. B