Datasheet AD7730, AD7730L (Analog Devices) - 9

AD7730/AD7730L Pin No. Mnemonic Function
18 STANDBY Logic Input. Taking this pin low shuts down the analog and digital circuitry, reducing current consumption to the 5 μA range. The on-chip registers retain all their values when the part is in standby mode. 19 CS Chip Select. Active low Logic Input used to select the AD7730. With this input hardwired low, the AD7730 can operate in its three-wire interface mode with SCLK, DIN and DOUT used to interface to the device. CS can be used to select the device in systems with more than one device on the serial bus or as a frame synchro- nization signal in communicating with the AD7730. 20 RDY Logic Output. Used as a status output in both conversion mode and calibration mode. In conversion mode, a logic low on this output indicates that a new output word is available from the AD7730 data register. The RDY pin will return high upon completion of a read operation of a full output word. If no data read has taken place after an output update, the RDY line will return high prior to the next output update, remain high while the update is taking place and return low again. This gives an indication of when a read operation should not be initiated to avoid initiating a read from the data register as it is being updated. In calibration mode, RDY goes high when calibration is initiated and it returns low to indicate that calibration is complete. A number of different events on the AD7730 set the RDY high and these are outlined in Table XVIII. 21 DOUT Serial Data Output with serial data being read from the output shift register on the part. This output shift register can contain information from the calibration registers, mode register, status register, filter register, DAC register or data register, depending on the register selection bits of the Communications Register. 22 DIN Serial Data Input with serial data being written to the input shift register on the part. Data from this input shift register is transferred to the calibration registers, mode register, communications register, DAC register or filter registers depending on the register selection bits of the Communications Register. 23 DVDD Digital Supply Voltage, +3 V or +5 V nominal. 24 DGND Ground reference point for digital circuitry.
TERMINOLOGY BIPOLAR NEGATIVE FULL-SCALE ERROR INTEGRAL NONLINEARITY
This is the deviation of the first code transition from the ideal This is the maximum deviation of any code from a straight line AIN(+) voltage (AIN(–) – VREF/GAIN + 0.5 LSB) when operat- passing through the endpoints of the transfer function. The end- ing in the bipolar mode. Negative full-scale error is a summation points of the transfer function are zero scale (not to be confused of zero error and gain error. with bipolar zero), a point 0.5 LSB below the first code transi- tion (000 . 000 to 000 . 001) and full scale, a point 0.5 LSB
POSITIVE FULL-SCALE OVERRANGE
above the last code transition (111 . 110 to 111 . 111). The Positive Full-Scale Overrange is the amount of overhead avail- error is expressed as a percentage of full scale. able to handle input voltages on AIN(+) input greater than AIN(–) + VREF/GAIN (for example, noise peaks or excess volt-
POSITIVE FULL-SCALE ERROR
ages due to system gain errors in system calibration routines) with- Positive Full-Scale Error is the deviation of the last code transition out introducing errors due to overloading the analog modulator (111 . 110 to 111 . 111) from the ideal AIN(+) voltage or overflowing the digital filter. (AIN(–) + VREF/GAIN – 3/2 LSBs). It applies to both unipolar and bipolar analog input ranges. Positive full-scale error is a
NEGATIVE FULL-SCALE OVERRANGE
summation of offset error and gain error. This is the amount of overhead available to handle voltages on AIN(+) below AIN(–) – VREF/GAIN without overloading the
UNIPOLAR OFFSET ERROR
analog modulator or overflowing the digital filter. Unipolar Offset Error is the deviation of the first code transition from the ideal AIN(+) voltage (AIN(–) + 0.5 LSB) when oper-
OFFSET CALIBRATION RANGE
ating in the unipolar mode. In the system calibration modes, the AD7730 calibrates its offset with respect to the analog input. The Offset Calibration
BIPOLAR ZERO ERROR
Range specification defines the range of voltages the AD7730 This is the deviation of the midscale transition (0111 . 111 to can accept and still accurately calibrate offset. 1000 . 000) from the ideal AIN(+) voltage (AIN(–) – 0.5 LSB) when operating in the bipolar mode.
FULL-SCALE CALIBRATION RANGE
This is the range of voltages that the AD7730 can accept in the
GAIN ERROR
system calibration mode and still calibrate full scale correctly. This is a measure of the span error of the ADC. It is a measure of the difference between the measured and the ideal span be-
INPUT SPAN
tween any two points in the transfer function. The two points In system calibration schemes, two voltages applied in sequence used to calculate the gain error are full scale and zero scale. to the AD7730’s analog input define the analog input range. The input span specification defines the minimum and maxi- mum input voltages, from zero to full scale, the AD7730 can accept and still accurately calibrate gain. REV. B –9–