Datasheet AD7811, AD7812 (Analog Devices) - 5

制造商Analog Devices
描述10-Bit, 8-Channel, 350 kSPS, Serial A/D Converter
页数 / 页24 / 5 — AD7811/AD7812. PIN CONFIGURATIONS. DIP/SOIC/TSSOP. REF. VDD. 20 V. 15 …
修订版C
文件格式/大小PDF / 336 Kb
文件语言英语

AD7811/AD7812. PIN CONFIGURATIONS. DIP/SOIC/TSSOP. REF. VDD. 20 V. 15 CONVST. CONVST. 14 SCLK. IN1. 18 SCLK. AD7811. AGND. 13 DIN. 17 DIN. TOP VIEW

AD7811/AD7812 PIN CONFIGURATIONS DIP/SOIC/TSSOP REF VDD 20 V 15 CONVST CONVST 14 SCLK IN1 18 SCLK AD7811 AGND 13 DIN 17 DIN TOP VIEW

该数据表的模型线

文件文字版本

AD7811/AD7812 PIN CONFIGURATIONS DIP/SOIC/TSSOP V 1 16 REF VDD V 1 20 V REF DD C 2 REF 15 CONVST C 2 19 REF CONVST V 3 14 SCLK IN1 V 3 18 SCLK IN1 AD7811 AGND 4 13 DIN AGND 4 17 DIN TOP VIEW V 5 12 IN2 (Not to Scale) DOUT VIN2 5 AD7812 16 DOUT V 6 TOP VIEW 11 RFS IN3 V 6 15 RFS IN3 (Not to Scale) VIN4 7 10 TFS VIN4 7 14 TFS A0 8 9 DGND V 8 13 IN5 DGND V 9 IN6 12 A0 V 10 11 IN7 VIN8 PIN FUNCTION DESCRIPTIONS Pin(s) Pin(s) AD7811 AD7812 Mnemonic Description
1 1 VREF An external reference input can be applied here. When using an external precision reference or VDD the EXTREF bit in the control register must be set to logic one. The external reference input range is 1.2 V to VDD. 2 2 CREF Reference Capacitor. A capacitor (10 nF) is connected here to improve the noise performance of the on-chip reference. 3, 5–7 3, 5–11 VIN1–VIN4(8) Analog Inputs. The analog input range is 0 V to VREF. 4 4 AGND Analog Ground. Ground reference for track/hold, comparator, on-chip reference and DAC. 8 12 A0 Package Address Pin. This Logic Input can be hardwired high or low. When used in conjunction with the package address bit in the control register this input allows two devices to share the same serial bus. For example a twelve channel solution can be achieved by using the AD7811 and the AD7812 on the same serial bus. 9 13 DGND Digital Ground. Ground reference for digital circuitry. 10 14 TFS Transmit Frame Sync. The falling edge of this Logic Input tells the part that a new control byte should be shifted in on the next 10 falling edges of SCLK. 11 15 RFS Receive Frame Sync. The rising edge of this Logic Input is used to enable a counter in the serial interface. It is used to provide compatibility with DSPs which use a continuous serial clock and framing signal. In multipackage applications the RFS Pin can also be used as a serial bus select pin. The serial interface will ignore the SCLK until it receives a rising edge on this input. The counter is reset at the end of a serial read operation. 12 16 DOUT Serial Data Output. Serial data is shifted out on this pin on the rising edge of the serial clock. The output enters a High impedance condition on the rising edge of the 11th SCLK pulse. 13 17 DIN Serial Data Input. The control byte is read in at this input. In order to complete a serial write operation 13 SCLK pulses need to be provided. Only the first 10 bits are shifted in—see Serial Interface section. 14 18 SCLK Serial Clock Input. An external serial clock is applied to this input to obtain serial data from the AD7811/AD7812 and also to latch data into the AD7811/AD7812. Data is clocked out on the rising edge of SCLK and latched in on the falling edge of SCLK. 15 19 CONVST Convert Start. This is an edge triggered logic input. The Track/Hold goes into its Hold Mode on the falling edge of this signal and a conversion is initiated. The state of this pin at the end of conversion also determines whether the part is powered down or not. See operating modes section of this data sheet. 16 20 VDD Positive Supply Voltage 2.7 V to 5.5 V. REV. B C –5– Document Outline Features General Description Product Highlights Functional Block Diagram Specifications Timing Characteristics Absolute Maximum Ratings ESD Caution Pin Configurations Pin Function Descriptions Terminology Signal to (Noise + Distortion) Ratio Total Harmonic Distortion Peak Harmonic or Spurious Noise Intermodulation Distortion Channel-to-Channel Isolation Relative Accuracy Differential Nonlinearity Offset Error Offset Error Match Gain Error Gain Error Match Track/Hold Acquisition Time Control Register (AD7811) Control Register (AD7812) Circuit Description Converter Operation Typical Connection Diagram Analog Input DC Acquisition Time AC Acquisition Time On-Chip Reference ADC Transfer Function Power-Down Options Power-On-Reset Power-Up Times Mode 2 Full Power-Down (PD1 = 1, PD0 = 0) Mode 2 Partial Power-Down (PD1 = 0, PD0 = 1) Power vs. Throughput Operating Modes Mode 1 Operation (High Speed Sampling) Mode 2 Operation (Automatic Power-Down) Serial Interface Simplifying the Serial Interface Microprocessor Interfacing AD7811/AD7812 to PIC16C6x/7x AD7811/AD7812 to MC68HC11 AD7811/AD7812 to 8051