Datasheet AD7811, AD7812 (Analog Devices) - 10

AD7811/AD7812 CIRCUIT DESCRIPTION SUPPLY 2.7V TO 5.5V Converter Operation THREE-WIRE
The AD7811 and AD7812 are successive approximation analog-
10
␮
F 0.1
␮
F 10nF SERIAL INTERFACE
to-digital converters based around a charge redistribution DAC. The ADCs can convert analog input signals in the range 0 V to
V VREF
V
DD CREF
DD. Figures 2 and 3 show simplified schematics of the ADC. Figure 2 shows the ADC during its acquisition phase. SW2 is
SCLK VIN1
closed and SW1 is in position A, the comparator is held in a
DOUT V
balanced condition and the sampling capacitor acquires the
IN2 AD7811/ 0V TO
signal on V
DIN µC/µP
IN.
VREF AD7812 INPUT VIN4(8) CONVST CHARGE REDISTRIBUTION DAC RFS SAMPLING CAPACITOR AGND A TFS VIN CONTROL SW1 DGND LOGIC A0 B ACQUISITION PHASE SW2 COMPARATOR AGND CLOCK
Figure 4. Typical Connection Diagram
OSC VDD/3 Analog Input
Figure 2. ADC Acquisition Phase Figure 5 shows an equivalent circuit of the analog input struc- ture of the AD7811 and AD7812. The two diodes D1 and D2 When the ADC starts a conversion, see Figure 3, SW2 will provide ESD protection for the analog inputs. Care must be open and SW1 will move to position B causing the comparator taken to ensure that the analog input signal never exceeds the to become unbalanced. The Control Logic and the Charge supply rails by more than 200 mV. This will cause these diodes Redistribution DAC are used to add and subtract fixed amounts to become forward biased and start conducting current into of charge from the sampling capacitor to bring the comparator the substrate. 20 mA is the maximum current these diodes can back into a balanced condition. When the comparator is rebal- conduct without causing irreversible damage to the part. How- anced, the conversion is complete. The Control Logic generates ever, it is worth noting that a small amount of current (1 mA) the ADC output code. Figure 10 shows the ADC transfer being conducted into the substrate due to an overvoltage on an function. unselected channel can cause inaccurate conversions on a selected channel. The capacitor C2 in Figure 5 is typically about
CHARGE
4 pF and can primarily be attributed to pin capacitance. The
REDISTRIBUTION DAC
resistor R1 is a lumped component made up of the on resistance
SAMPLING
of a multiplexer and a switch. This resistor is typically about
CAPACITOR A V
125 Ω. The capacitor C1 is the ADC sampling capacitor and
IN CONTROL SW1 LOGIC
has a capacitance of 3.5 pF.
B CONVERSION PHASE COMPARATOR SW2 V AGND DD CLOCK OSC VDD/3 D1 C1
Figure 3. ADC Conversion Phase
R1 3.5pF 125
⍀
VIN VDD /3 TYPICAL CONNECTION DIAGRAM C2
Figure 4 shows a typical connection diagram for the AD7811/
D2 4pF
AD7812. The AGND and DGND are connected together at
CONVERSION PHASE – SWITCH OPEN TRACK PHASE – SWITCH CLOSED
the device for good noise suppression. The serial interface is implemented using three wires with RFS/TFS connected to CONVST see Serial Interface section for more details. VREF is Figure 5. Equivalent Analog Input Circuit connected to a well decoupled VDD pin to provide an analog The analog inputs on the AD7811 and AD7812 can be config- input range of 0 V to VDD. If the AD7811 or AD7812 is not ured as single ended with respect to analog ground (AGND), sharing a serial bus with another AD7811 or AD7812 then A0 as pseudo differential with respect to a common, and also as (package address pin) should be hardwired low. The default pseudo differential pairs—see Control Register section. power up value of the package address bit in the control register is 0. For applications where power consumption is of concern, the automatic power down at the end of a conversion should be used to improve power performance. See Power-Down Options section of the data sheet. –10– REV. B C Document Outline Features General Description Product Highlights Functional Block Diagram Specifications Timing Characteristics Absolute Maximum Ratings ESD Caution Pin Configurations Pin Function Descriptions Terminology Signal to (Noise + Distortion) Ratio Total Harmonic Distortion Peak Harmonic or Spurious Noise Intermodulation Distortion Channel-to-Channel Isolation Relative Accuracy Differential Nonlinearity Offset Error Offset Error Match Gain Error Gain Error Match Track/Hold Acquisition Time Control Register (AD7811) Control Register (AD7812) Circuit Description Converter Operation Typical Connection Diagram Analog Input DC Acquisition Time AC Acquisition Time On-Chip Reference ADC Transfer Function Power-Down Options Power-On-Reset Power-Up Times Mode 2 Full Power-Down (PD1 = 1, PD0 = 0) Mode 2 Partial Power-Down (PD1 = 0, PD0 = 1) Power vs. Throughput Operating Modes Mode 1 Operation (High Speed Sampling) Mode 2 Operation (Automatic Power-Down) Serial Interface Simplifying the Serial Interface Microprocessor Interfacing AD7811/AD7812 to PIC16C6x/7x AD7811/AD7812 to MC68HC11 AD7811/AD7812 to 8051