Datasheet AD7813 (Analog Devices) - 8

AD7813
During the acquisition phase the sampling capacitor must be
MODE 1
charged to within a 1/2 LSB of its final value. The time it takes
V
to charge the sampling capacitor (T
DD
CHARGE) is given by the following formula:
EXT CONVST
T
t
CHARGE = 7.6 × (R2 + 125 Ω) × 3.5 pF
POWER-UP 1.5 s
For small values of source impedance, the settling time associ- ated with the sampling circuit (100 ns) is, in effect, the acquisi-
INT CONVST
tion time of the ADC. For example, with a source impedance (R2) of 10 Ω the charge time for the sampling capacitor is
MODE 2
approximately 4 ns. The charge time becomes significant for
V
source impedances of 2 kΩ and greater.
DD AC Acquisition Time EXT CONVST
In ac applications it is recommended to always buffer analog
t t POWER-UP POWER-UP 1.5 s
input signals. The source impedance of the drive circuitry must
1.5 s
be kept as low as possible to minimize the acquisition time of
INT CONVST
the ADC. Large values of source impedance will cause the THD to degrade at high throughput rates. Figure 8. Power-Up Times
ADC TRANSFER FUNCTION POWER VS. THROUGHPUT RATE
The output coding of the AD7813 is straight binary. The By operating the AD7813 in Mode 2, the average power con- designed code transitions occur at successive integer LSB values sumption of the AD7813 decreases at lower throughput rates. (i.e., 1 LSB, 2 LSBs, etc.). The LSB size is = VREF/1024. The Figure 9 shows how the Automatic Power-Down is implemented ideal transfer characteristic for the AD7813 is shown in Figure 7. using the external CONVST signal to achieve the optimum power performance for the AD7813. The AD7813 is operated in Mode 2, and the duration of the external CONVST pulse is
111...111
set to be equal to or less than the power-up time of the device.
111...110
As the throughput rate is reduced, the device remains in its power-
111...000
down state longer and the average power consumption over time
1LSB = VREF/1024
drops accordingly.
011...111 ADC CODE 000...010 EXT CONVST 000...001 000...000 t POWER-UP 1LSB 0V +VREF–1LSB 1.5 s t CONVERT ANALOG INPUT POWER-DOWN 2.3 s
Figure 7. Transfer Characteristic
INT CONVST t CYCLE POWER-UP TIMES 100 s @ 10kSPS
The AD7813 has a 1.5 µs power-up time. When VDD is first Figure 9. Automatic Power-Down connected, the AD7813 is in a low current mode of operation. In order to carry out a conversion the AD7813 must first be For example, if the AD7813 is operated in a continuous sam- powered up. The ADC is powered up by a rising edge on an pling mode, with a throughput rate of 10 kSPS, the power con- internally generated CONVST signal, which occurs as a result sumption is calculated as follows. The power dissipation during of a rising edge on the external CONVST pin. The rising edge normal operation is 10.5 mW, VDD = 3 V. If the power-up time of the external CONVST signal initiates a 1.5 µs pulse on the is 1.5 µs and the conversion time is 2.3 µs, the AD7813 can then internal CONVST signal. This pulse is present to ensure the be said to dissipate 10.5 mW for 3.8 µs (worst-case) during each part has enough time to power up before a conversion is initi- conversion cycle. If the throughput rate is 10 kSPS, the cycle ated, as a conversion is initiated on the falling edge of gated time is 100 µs and the average power dissipated during each CONVST. See Timing and Control section. Care must be taken cycle is (3.8/100) × (10.5 mW) = 400 µW. to ensure that the CONVST pin of the AD7813 is logic low when VDD is first applied. When operating in Mode 2, the ADC is powered down at the end of each conversion and powered up again before the next conversion is initiated. (See Figure 8.) REV. C –7–