Datasheet AD9200 (Analog Devices) - 10

制造商Analog Devices
描述10-Bit, 20 MSPS, 80 mW CMOS A/D Converter
页数 / 页25 / 10 — AD9200. SUMMARY OF MODES VOLTAGE REFERENCE. AIN. A/D. 1 V Mode. SHA. …
修订版E
文件格式/大小PDF / 378 Kb
文件语言英语

AD9200. SUMMARY OF MODES VOLTAGE REFERENCE. AIN. A/D. 1 V Mode. SHA. REFTS. CORE. 2 V Mode. External Divider Mode. REFBS

AD9200 SUMMARY OF MODES VOLTAGE REFERENCE AIN A/D 1 V Mode SHA REFTS CORE 2 V Mode External Divider Mode REFBS

该数据表的模型线

文件文字版本

AD9200 SUMMARY OF MODES VOLTAGE REFERENCE AIN A/D 1 V Mode
the internal reference may be set to 1 V by connect-
SHA REFTS CORE
ing REFSENSE and VREF together.
2 V Mode
the internal reference my be set to 2 V by connecting REFSENSE to analog ground
AD9200 External Divider Mode
the internal reference may be set to a
REFBS
point between 1 V and 2 V by adding external resistors. See Figure 16f.
External Reference Mode
enables the user to apply an exter- Figure 15. AD9200 Equivalent Functional Input Circuit nal reference to REFTS, REFBS and VREF pins. This mode In single-ended operation, the input spans the range, is attained by tying REFSENSE to VDD. REFBS ≤ AIN ≤ REFTS
REFERENCE BUFFER
where REFBS can be connected to GND and REFTS con-
Center Span Mode
midscale is set by shorting REFTS and nected to VREF. If the user requires a different reference range, REFBS together and applying the midscale voltage to that point REFBS and REFTS can be driven to any voltage within the The MODE pin is set to AVDD/2. The analog input will swing power supply rails, so long as the difference between the two is about that midscale point. between 1 V and 2 V.
Top/Bottom Mode
sets the input range between two points. In differential operation, REFTS and REFBS are shorted to- The two points are between 1 V and 2 V apart. The Top/Bottom gether, and the input span is set by VREF, Mode is enabled by tying the MODE pin to AVDD. (REFTS – VREF/2) ≤ AIN ≤ (REFTS + VREF/2) where VREF is determined by the internal reference or brought
ANALOG INPUT Differential Mode
is attained by driving the AIN pin as one in externally by the user. differential input and shorting REFTS and REFBS together and The best noise performance may be obtained by operating the driving them as the second differential input. The MODE pin AD9200 with a 2 V input range. The best distortion perfor- is tied to AVDD/2. Preferred mode for optimal distortion mance may be obtained by operating the AD9200 with a 1 V performance. input range.
Single-Ended
is attained by driving the AIN pin while the REFTS and REFBS pins are held at dc points. The MODE pin is
REFERENCE OPERATION
tied to AVDD. The AD9200 can be configured in a variety of reference topolo- gies. The simplest configuration is to use the AD9200’s onboard
Single-Ended/Clamped (AC Coupled)
the input may be bandgap reference, which provides a pin-strappable option to clamped to some dc level by ac coupling the input. This is done generate either a 1 V or 2 V output. If the user desires a refer- by tying the CLAMPIN to some dc point and applying a pulse ence voltage other than those two, an external resistor divider to the CLAMP pin. MODE pin is tied to AVDD. can be connected between VREF, REFSENSE and analog ground to generate a potential anywhere between 1 V and 2 V.
SPECIAL
Another alternative is to use an external reference for designs
AD876 Mode
enables users of the AD876 to drop the AD9200 requiring enhanced accuracy and/or drift performance. A into their socket. This mode is attained by floating or grounding third alternative is to bring in top and bottom references, the MODE pin. bypassing VREF altogether. Figures 16d, 16e and 16f illustrate the reference and input ar-
INPUT AND REFERENCE OVERVIEW
Figure 16, a simplified model of the AD9200, highlights the chitecture of the AD9200. In tailoring a desired arrangement, relationship between the analog input, AIN, and the reference the user can select an input configuration to match drive circuit. voltages, REFTS, REFBS and VREF. Like the voltages applied Then, moving to the reference modes at the bottom of the to the resistor ladder in a flash A/D converter, REFTS and figure, select a reference circuit to accommodate the offset and REFBS define the maximum and minimum input voltages to amplitude of a full-scale signal. the A/D. Table I outlines pin configurations to match user requirements. The input stage is normally configured for single-ended opera- tion, but allows for differential operation by shorting REFTS and REFBS together to be used as the second input. REV. E –9–