Datasheet AD7810 (Analog Devices) - 8
| 制造商 | Analog Devices |
| 描述 | 2.7 V to 5.5 V, 2 ms, 10-Bit ADC in 8-Lead microSOIC/DIP |
| 页数 / 页 | 12 / 8 — AD7810. AC Acquisition Time. VDD. VIN+. RSENSE. VIN–. ADC TRANSFER … |
| 修订版 | B |
| 文件格式/大小 | PDF / 185 Kb |
| 文件语言 | 英语 |
AD7810. AC Acquisition Time. VDD. VIN+. RSENSE. VIN–. ADC TRANSFER FUNCTION. DC Acquisition Time. 111...111. 111...110. 111...000. 011...111
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文件文字版本
AD7810
When using the pseudo differential input scheme, the signal on For small values of source impedance, the settling time associated VIN– must not vary by more than a 1/2 LSB during the conver- with the sampling circuit (100 ns) is, in effect, the acquisition sion process. If the signal on VIN– varies during conversion, the time of the ADC. For example, with a source impedance (R2) conversion result will be incorrect. For single-ended operation, of 10 Ω, the charge time for the sampling capacitor is approxi- VIN– is always connected to AGND. Figure 9 shows the AD7810 mately 4 ns. The charge time becomes significant for source pseudo differential input being used to make a unipolar dc cur- impedances of 2 kΩ and greater. rent measurement. A sense resistor is used to convert the current
AC Acquisition Time
to a voltage and the voltage, is applied to the differential input In ac applications it is recommended to always buffer analog as shown. input signals. The source impedance of the drive circuitry must be kept as low as possible to minimize the acquisition time of
VDD
the ADC. Large values of source impedance will cause the THD to degrade at high throughput rates. In addition, better perfor-
VIN+
mance can generally be achieved by using an external 1 nF
RSENSE AD7810
capacitor on VIN+.
VIN– RL ADC TRANSFER FUNCTION
The output coding of the AD7810 is straight binary. The designed code transitions occur at successive integer LSB values Figure 9. DC Current Measurement Scheme (i.e., 1 LSB, 2 LSBs, etc.). The LSB size is = VREF/1024. The
DC Acquisition Time
ideal transfer characteristic for the AD7810 is shown in Figure The ADC starts a new acquisition phase at the end of a conver- 11 below. sion and ends on the falling edge of the CONVST signal. At the end of a conversion there is a settling time associated with the
111...111
sampling circuit. This settling time lasts approximately 100 ns. The analog signal on V
111...110
IN+ is also being acquired during this settling time; therefore, the minimum acquisition time needed is approximately 100 ns. Figure 10 shows the equivalent charging circuit for the sampling capacitor when the ADC is in its acquisition phase. R2 repre-
111...000
sents the source impedance of a buffer amplifier or resistive
011...111 ADC CODE
network; R1 is an internal multiplexer resistance and C1 is the
1LSB = VREF/1024
sampling capacitor.
000...010 R1 V 000...001 IN+ R2 125
⍀
000...000 C1 0V 1LSB +V 3.5pF REF –1LSB ANALOG INPUT
Figure 11. Transfer Characteristic Figure 10. Equivalent Sampling Circuit During the acquisition phase, the sampling capacitor must be charged to within a 1/2 LSB of its final value. The time it takes to charge the sampling capacitor (tCHARGE) is given by the fol- lowing formula: tCHARGE = 7.6 × (R2 + 125 Ω) × 3.5 pF REV. B –7–
When using the pseudo differential input scheme, the signal on For small values of source impedance, the settling time associated VIN– must not vary by more than a 1/2 LSB during the conver- with the sampling circuit (100 ns) is, in effect, the acquisition sion process. If the signal on VIN– varies during conversion, the time of the ADC. For example, with a source impedance (R2) conversion result will be incorrect. For single-ended operation, of 10 Ω, the charge time for the sampling capacitor is approxi- VIN– is always connected to AGND. Figure 9 shows the AD7810 mately 4 ns. The charge time becomes significant for source pseudo differential input being used to make a unipolar dc cur- impedances of 2 kΩ and greater. rent measurement. A sense resistor is used to convert the current
AC Acquisition Time
to a voltage and the voltage, is applied to the differential input In ac applications it is recommended to always buffer analog as shown. input signals. The source impedance of the drive circuitry must be kept as low as possible to minimize the acquisition time of
VDD
the ADC. Large values of source impedance will cause the THD to degrade at high throughput rates. In addition, better perfor-
VIN+
mance can generally be achieved by using an external 1 nF
RSENSE AD7810
capacitor on VIN+.
VIN– RL ADC TRANSFER FUNCTION
The output coding of the AD7810 is straight binary. The designed code transitions occur at successive integer LSB values Figure 9. DC Current Measurement Scheme (i.e., 1 LSB, 2 LSBs, etc.). The LSB size is = VREF/1024. The
DC Acquisition Time
ideal transfer characteristic for the AD7810 is shown in Figure The ADC starts a new acquisition phase at the end of a conver- 11 below. sion and ends on the falling edge of the CONVST signal. At the end of a conversion there is a settling time associated with the
111...111
sampling circuit. This settling time lasts approximately 100 ns. The analog signal on V
111...110
IN+ is also being acquired during this settling time; therefore, the minimum acquisition time needed is approximately 100 ns. Figure 10 shows the equivalent charging circuit for the sampling capacitor when the ADC is in its acquisition phase. R2 repre-
111...000
sents the source impedance of a buffer amplifier or resistive
011...111 ADC CODE
network; R1 is an internal multiplexer resistance and C1 is the
1LSB = VREF/1024
sampling capacitor.
000...010 R1 V 000...001 IN+ R2 125
⍀
000...000 C1 0V 1LSB +V 3.5pF REF –1LSB ANALOG INPUT
Figure 11. Transfer Characteristic Figure 10. Equivalent Sampling Circuit During the acquisition phase, the sampling capacitor must be charged to within a 1/2 LSB of its final value. The time it takes to charge the sampling capacitor (tCHARGE) is given by the fol- lowing formula: tCHARGE = 7.6 × (R2 + 125 Ω) × 3.5 pF REV. B –7–